Lines Matching defs:itv
29 static void ivtv_pcm_work_handler(struct ivtv *itv)
31 struct ivtv_stream *s = &itv->streams[IVTV_ENC_STREAM_TYPE_PCM];
50 itv->pcm_announce_callback(itv->alsa,
58 static void ivtv_pio_work_handler(struct ivtv *itv)
60 struct ivtv_stream *s = &itv->streams[itv->cur_pio_stream];
65 if (itv->cur_pio_stream < 0 || itv->cur_pio_stream >= IVTV_MAX_STREAMS ||
67 itv->cur_pio_stream = -1;
78 memcpy_fromio(buf->buf, itv->dec_mem + s->sg_processing[i].src - IVTV_DECODER_OFFSET, size);
81 memcpy_fromio(buf->buf, itv->enc_mem + s->sg_processing[i].src, size);
92 struct ivtv *itv = container_of(work, struct ivtv, irq_work);
94 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags))
95 ivtv_pio_work_handler(itv);
97 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags))
98 ivtv_vbi_work_handler(itv);
100 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags))
101 ivtv_yuv_work_handler(itv);
103 if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PCM, &itv->i_flags))
104 ivtv_pcm_work_handler(itv);
113 struct ivtv *itv = s->itv;
153 if (itv->has_cx23415)
158 size = itv->vbi.enc_size * itv->vbi.fpi;
159 offset = read_enc(itv->vbi.enc_start - 4) + 12;
168 size = read_dec(itv->vbi.dec_start + 4) + 8;
169 offset = read_dec(itv->vbi.dec_start) + itv->vbi.dec_start;
180 if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
248 struct ivtv *itv = s->itv;
280 if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
305 ivtv_process_vbi_data(itv, buf, 0, s->type);
317 itv->pcm_announce_callback != NULL) {
329 set_bit(IVTV_F_I_WORK_HANDLER_PCM, &itv->i_flags);
330 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
339 struct ivtv *itv = s->itv;
340 struct yuv_playback_info *yi = &itv->yuv_info;
400 spin_lock_irqsave(&itv->dma_reg_lock, flags);
401 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))
405 spin_unlock_irqrestore(&itv->dma_reg_lock, flags);
407 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))
416 struct ivtv *itv = s->itv;
426 itv->dma_timer.expires = jiffies + msecs_to_jiffies(300);
427 add_timer(&itv->dma_timer);
432 struct ivtv *itv = s->itv;
442 itv->dma_timer.expires = jiffies + msecs_to_jiffies(300);
443 add_timer(&itv->dma_timer);
449 struct ivtv *itv = s->itv;
450 struct ivtv_stream *s_vbi = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
495 set_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags);
496 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
497 set_bit(IVTV_F_I_PIO, &itv->i_flags);
498 itv->cur_pio_stream = s->type;
501 itv->dma_retries = 0;
503 set_bit(IVTV_F_I_DMA, &itv->i_flags);
504 itv->cur_dma_stream = s->type;
510 struct ivtv *itv = s->itv;
521 itv->dma_retries = 0;
523 set_bit(IVTV_F_I_DMA, &itv->i_flags);
524 itv->cur_dma_stream = s->type;
527 static void ivtv_irq_dma_read(struct ivtv *itv)
535 del_timer(&itv->dma_timer);
537 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) && itv->cur_dma_stream < 0)
540 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
541 s = &itv->streams[itv->cur_dma_stream];
547 s->sg_processed, s->sg_processing_size, itv->dma_retries);
549 if (itv->dma_retries == 3) {
551 itv->dma_retries = 0;
558 itv->dma_retries++;
576 ivtv_vapi(itv, CX2341X_DEC_SCHED_DMA_FROM_HOST, 3, 0, s->q_dma.bytesused,
586 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
587 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
588 itv->cur_dma_stream = -1;
589 wake_up(&itv->dma_waitq);
592 static void ivtv_irq_enc_dma_complete(struct ivtv *itv)
597 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, 2, data);
598 IVTV_DEBUG_HI_IRQ("ENC DMA COMPLETE %x %d (%d)\n", data[0], data[1], itv->cur_dma_stream);
600 del_timer(&itv->dma_timer);
602 if (itv->cur_dma_stream < 0)
605 s = &itv->streams[itv->cur_dma_stream];
610 s->dma_offset, s->sg_processed, s->sg_processing_size, itv->dma_retries);
612 if (itv->dma_retries == 3) {
614 itv->dma_retries = 0;
621 itv->dma_retries++;
629 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
630 itv->cur_dma_stream = -1;
633 s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
638 wake_up(&itv->dma_waitq);
641 static void ivtv_irq_enc_pio_complete(struct ivtv *itv)
645 if (itv->cur_pio_stream < 0 || itv->cur_pio_stream >= IVTV_MAX_STREAMS) {
646 itv->cur_pio_stream = -1;
649 s = &itv->streams[itv->cur_pio_stream];
651 clear_bit(IVTV_F_I_PIO, &itv->i_flags);
652 itv->cur_pio_stream = -1;
655 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 0);
657 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 1);
659 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 2);
660 clear_bit(IVTV_F_I_PIO, &itv->i_flags);
662 s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
665 wake_up(&itv->dma_waitq);
668 static void ivtv_irq_dma_err(struct ivtv *itv)
673 del_timer(&itv->dma_timer);
675 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, 2, data);
678 status, itv->cur_dma_stream);
692 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) &&
693 itv->cur_dma_stream >= 0 && itv->cur_dma_stream < IVTV_MAX_STREAMS) {
694 struct ivtv_stream *s = &itv->streams[itv->cur_dma_stream];
710 itv->dma_timer.expires =
712 add_timer(&itv->dma_timer);
716 if (itv->dma_retries < 3) {
724 itv->dma_retries++;
732 if (test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
733 ivtv_udma_start(itv);
736 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
737 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
738 itv->cur_dma_stream = -1;
739 wake_up(&itv->dma_waitq);
742 static void ivtv_irq_enc_start_cap(struct ivtv *itv)
748 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA, 7, data);
756 s = &itv->streams[ivtv_stream_map[data[0]]];
762 static void ivtv_irq_enc_vbi_cap(struct ivtv *itv)
768 s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
774 static void ivtv_irq_dec_vbi_reinsert(struct ivtv *itv)
777 struct ivtv_stream *s = &itv->streams[IVTV_DEC_STREAM_TYPE_VBI];
786 static void ivtv_irq_dec_data_req(struct ivtv *itv)
793 if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) {
794 ivtv_api_get_data(&itv->dec_mbox, IVTV_MBOX_DMA, 2, data);
795 itv->dma_data_req_size =
796 1080 * ((itv->yuv_info.v4l2_src_h + 31) & ~31);
797 itv->dma_data_req_offset = data[1];
798 if (atomic_read(&itv->yuv_info.next_dma_frame) >= 0)
799 ivtv_yuv_frame_complete(itv);
800 s = &itv->streams[IVTV_DEC_STREAM_TYPE_YUV];
803 ivtv_api_get_data(&itv->dec_mbox, IVTV_MBOX_DMA, 3, data);
804 itv->dma_data_req_size = min_t(u32, data[2], 0x10000);
805 itv->dma_data_req_offset = data[1];
806 s = &itv->streams[IVTV_DEC_STREAM_TYPE_MPG];
809 itv->dma_data_req_offset, itv->dma_data_req_size);
810 if (itv->dma_data_req_size == 0 || s->q_full.bytesused < itv->dma_data_req_size) {
814 if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags))
815 ivtv_yuv_setup_stream_frame(itv);
817 ivtv_queue_move(s, &s->q_full, NULL, &s->q_predma, itv->dma_data_req_size);
818 ivtv_dma_stream_dec_prepare(s, itv->dma_data_req_offset + IVTV_DECODER_OFFSET, 0);
822 static void ivtv_irq_vsync(struct ivtv *itv)
832 struct yuv_playback_info *yi = &itv->yuv_info;
839 ((itv->last_vsync_field & 1) ^ f->sync_field)) ||
840 (frame != (itv->last_vsync_field & 1) && !f->interlaced)) {
856 if (frame != (itv->last_vsync_field & 1)) {
865 struct ivtv_stream *s = ivtv_get_output_stream(itv);
867 itv->last_vsync_field += 1;
869 clear_bit(IVTV_F_I_VALID_DEC_TIMINGS, &itv->i_flags);
870 clear_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);
873 set_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);
875 if (test_bit(IVTV_F_I_EV_VSYNC_ENABLED, &itv->i_flags)) {
876 set_bit(IVTV_F_I_EV_VSYNC, &itv->i_flags);
877 wake_up(&itv->event_waitq);
883 wake_up(&itv->vsync_waitq);
886 if (frame && (itv->output_mode == OUT_PASSTHROUGH ||
887 test_bit(IVTV_F_I_UPDATE_WSS, &itv->i_flags) ||
888 test_bit(IVTV_F_I_UPDATE_VPS, &itv->i_flags) ||
889 test_bit(IVTV_F_I_UPDATE_CC, &itv->i_flags))) {
890 set_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags);
891 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
907 set_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags);
908 set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
920 struct ivtv *itv = (struct ivtv *)dev_id;
926 spin_lock(&itv->dma_reg_lock);
930 combo = ~itv->irqmask & stat;
939 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
941 if ((itv->last_vsync_field & 1) !=
952 spin_unlock(&itv->dma_reg_lock);
967 ivtv_irq_dma_read(itv);
971 ivtv_irq_enc_dma_complete(itv);
975 ivtv_irq_enc_pio_complete(itv);
979 ivtv_irq_dma_err(itv);
983 ivtv_irq_enc_start_cap(itv);
987 ivtv_irq_enc_vbi_cap(itv);
991 ivtv_irq_dec_vbi_reinsert(itv);
996 set_bit(IVTV_F_I_EOS, &itv->i_flags);
997 wake_up(&itv->eos_waitq);
1001 ivtv_irq_dec_data_req(itv);
1005 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
1006 ivtv_irq_vsync(itv);
1011 /*ivtv_vapi(itv, CX2341X_ENC_REFRESH_INPUT, 0); */
1018 if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_DMA, &itv->i_flags)) {
1019 itv->irq_rr_idx++;
1021 int idx = (i + itv->irq_rr_idx) % IVTV_MAX_STREAMS;
1022 struct ivtv_stream *s = &itv->streams[idx];
1034 test_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags))
1035 ivtv_udma_start(itv);
1038 if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_PIO, &itv->i_flags)) {
1039 itv->irq_rr_idx++;
1041 int idx = (i + itv->irq_rr_idx) % IVTV_MAX_STREAMS;
1042 struct ivtv_stream *s = &itv->streams[idx];
1052 if (test_and_clear_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags)) {
1053 kthread_queue_work(&itv->irq_worker, &itv->irq_work);
1056 spin_unlock(&itv->dma_reg_lock);
1067 struct ivtv *itv = from_timer(itv, t, dma_timer);
1069 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))
1071 IVTV_ERR("DMA TIMEOUT %08x %d\n", read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
1074 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
1075 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
1076 itv->cur_dma_stream = -1;
1077 wake_up(&itv->dma_waitq);