Lines Matching refs:base_addr

737 	itv->base_addr = pci_resource_start(itv->pdev, 0);
844 if (!request_mem_region(itv->base_addr, IVTV_ENCODER_SIZE, "ivtv encoder")) {
849 if (!request_mem_region(itv->base_addr + IVTV_REG_OFFSET,
852 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE);
857 !request_mem_region(itv->base_addr + IVTV_DECODER_OFFSET,
860 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE);
861 release_mem_region(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE);
874 release_mem_region(itv->base_addr + IVTV_DECODER_OFFSET,
876 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE);
877 release_mem_region(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE);
900 pdev->irq, pci_latency, (u64)itv->base_addr);
1032 IVTV_DEBUG_INFO("base addr: 0x%llx\n", (u64)itv->base_addr);
1043 (u64)itv->base_addr + IVTV_ENCODER_OFFSET, IVTV_ENCODER_SIZE);
1044 itv->enc_mem = ioremap(itv->base_addr + IVTV_ENCODER_OFFSET,
1057 (u64)itv->base_addr + IVTV_DECODER_OFFSET, IVTV_DECODER_SIZE);
1058 itv->dec_mem = ioremap(itv->base_addr + IVTV_DECODER_OFFSET,
1075 (u64)itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE);
1077 ioremap(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE);
1283 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE);
1284 release_mem_region(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE);
1286 release_mem_region(itv->base_addr + IVTV_DECODER_OFFSET, IVTV_DECODER_SIZE);
1444 release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE);
1445 release_mem_region(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE);
1447 release_mem_region(itv->base_addr + IVTV_DECODER_OFFSET, IVTV_DECODER_SIZE);