pci/dt3155/dt3155.c

40 	iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2);
47 		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
70 	iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
76 		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
96 	iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
116 		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
154 	iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
155 	iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
156 	iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
157 	iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
159 	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
161 	iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
182 	iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
185 	iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
244 		iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
250 		iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
267 		iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
268 		iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);
269 		iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);
270 		iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);
274 	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
416 	iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN |
421 	iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
422 	iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
423 	iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
424 	iowrite32(0x00000020, pd->regs + FIFO_TRIGGER);
425 	iowrite32(0x00000103, pd->regs + XFER_MODE);
426 	iowrite32(0, pd->regs + RETRY_WAIT_CNT);
427 	iowrite32(0, pd->regs + INT_CSR);
428 	iowrite32(1, pd->regs + EVEN_FLD_MASK);
429 	iowrite32(1, pd->regs + ODD_FLD_MASK);
430 	iowrite32(0, pd->regs + MASK_LENGTH);
431 	iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
432 	iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
471 	iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,