pci/cx18/cx18-av-core.c

15 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
20 	u32 x = cx18_read_reg(cx, reg);
23 	cx18_write_reg(cx, x, reg);
27 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
31 	u32 x = cx18_read_reg(cx, reg);
34 	cx18_write_reg_expect(cx, x, reg,
39 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
41 	cx18_write_reg(cx, value, 0xc40000 + addr);
46 cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
48 	cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
52 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
54 	cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
58 u8 cx18_av_read(struct cx18 *cx, u16 addr)
60 	u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
66 u32 cx18_av_read4(struct cx18 *cx, u16 addr)
68 	return cx18_read_reg(cx, 0xc40000 + addr);
71 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
74 	return cx18_av_write(cx, addr,
75 			     (cx18_av_read(cx, addr) & and_mask) |
79 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
82 	return cx18_av_write4(cx, addr,
83 			     (cx18_av_read4(cx, addr) & and_mask) |
87 static void cx18_av_init(struct cx18 *cx)
99 	cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
103 	cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
107 	cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
110 	cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
116 	struct cx18 *cx = v4l2_get_subdevdata(sd);
120 	cx18_av_loadfw(cx);
122 	cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
126 	v = cx18_av_read4(cx, CXADEC_HOST_REG1);
128 	cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
130 	cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
134 	v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
136 	cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
138 	cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
140 	v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
142 	cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
144 	cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
147 	cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
149 	v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
151 	cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
153 	cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
157 	cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
160 	cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
163 	cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
164 	cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
181 	cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000);
184 	cx18_av_init(cx);
189 	cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
193 	cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
196 	cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
205 	cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
228 	cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00);
235 	cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
236 	default_volume = cx18_av_read(cx, 0x8d4);
244 		cx18_av_write(cx, 0x8d4, 228);
248 		cx18_av_write(cx, 0x8d4, 20);
273 void cx18_av_std_setup(struct cx18 *cx)
275 	struct cx18_av_state *state = &cx->av_state;
292 		cx18_av_write(cx, 0x49f, 0x11);
294 		cx18_av_write(cx, 0x49f, 0x14);
440 	pll_int = cx18_av_read(cx, 0x108);
441 	pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
442 	pll_post = cx18_av_read(cx, 0x109);
476 	cx18_av_write(cx, 0x470, hblank);
477 	cx18_av_write(cx, 0x471,
479 	cx18_av_write(cx, 0x472, hactive >> 4);
482 	cx18_av_write(cx, 0x473, burst);
485 	cx18_av_write(cx, 0x474, vblank);
486 	cx18_av_write(cx, 0x475,
488 	cx18_av_write(cx, 0x476, vactive >> 4);
489 	cx18_av_write(cx, 0x477, vblank656);
492 	cx18_av_write(cx, 0x478, src_decimation & 0xff);
493 	cx18_av_write(cx, 0x479, (src_decimation >> 8) & 0xff);
496 	cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
499 	cx18_av_write(cx, 0x47b, comb);
502 	cx18_av_write(cx, 0x47c, sc);
503 	cx18_av_write(cx, 0x47d, (sc >> 8) & 0xff);
504 	cx18_av_write(cx, 0x47e, (sc >> 16) & 0xff);
513 	cx18_av_write(cx, 0x47f, state->slicer_line_delay);
516 static void input_change(struct cx18 *cx)
518 	struct cx18_av_state *state = &cx->av_state;
523 	cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
524 	cx18_av_and_or(cx, 0x401, ~0x60, 0);
525 	cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
530 			cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
531 			cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
534 			cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
535 			cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
538 			cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
539 			cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
543 		cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
544 		cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
547 		cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
548 		cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
551 	v = cx18_av_read(cx, 0x803);
555 		cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
557 		cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
564 	struct cx18 *cx = v4l2_get_subdevdata(sd);
565 	input_change(cx);
569 static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
572 	struct cx18_av_state *state = &cx->av_state;
676 	cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7);
678 	cx18_av_and_or(cx, 0x401, ~0x6, input_mode);
681 	adc2_cfg = cx18_av_read(cx, 0x102);
692 	cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17);
695 	afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL);
733 	cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg);
737 	cx18_av_audio_set_path(cx);
738 	input_change(cx);
746 	struct cx18 *cx = v4l2_get_subdevdata(sd);
747 	return set_input(cx, input, state->aud_input);
754 	struct cx18 *cx = v4l2_get_subdevdata(sd);
755 	return set_input(cx, state->vid_input, input);
761 	struct cx18 *cx = v4l2_get_subdevdata(sd);
769 	vpres = cx18_av_read(cx, 0x40e) & 0x20;
776 	mode = cx18_av_read(cx, 0x804);
798 	struct cx18 *cx = v4l2_get_subdevdata(sd);
804 	v = cx18_av_read(cx, 0x809);
835 	cx18_av_write_expect(cx, 0x809, v, v, 0xff);
843 	struct cx18 *cx = v4l2_get_subdevdata(sd);
885 		cx18_av_and_or(cx, 0x400, ~0xf, 1);
887 		cx18_av_and_or(cx, 0x47b, ~6, 0);
889 	cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
890 	cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
891 	cx18_av_std_setup(cx);
892 	input_change(cx);
906 	struct cx18 *cx = v4l2_get_subdevdata(sd);
910 		cx18_av_write(cx, 0x414, ctrl->val - 128);
914 		cx18_av_write(cx, 0x415, ctrl->val << 1);
918 		cx18_av_write(cx, 0x420, ctrl->val << 1);
919 		cx18_av_write(cx, 0x421, ctrl->val << 1);
923 		cx18_av_write(cx, 0x422, ctrl->val);
938 	struct cx18 *cx = v4l2_get_subdevdata(sd);
948 	Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
949 	Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
951 	Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
952 	Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
998 	cx18_av_write(cx, 0x418, HSC & 0xff);
999 	cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
1000 	cx18_av_write(cx, 0x41a, HSC >> 16);
1002 	cx18_av_write(cx, 0x41c, VSC & 0xff);
1003 	cx18_av_write(cx, 0x41d, VSC >> 8);
1005 	cx18_av_write(cx, 0x41e, 0x8 | filter);
1011 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1015 		cx18_av_write(cx, 0x115, 0x8c);
1016 		cx18_av_write(cx, 0x116, 0x07);
1018 		cx18_av_write(cx, 0x115, 0x00);
1019 		cx18_av_write(cx, 0x116, 0x00);
1024 static void log_video_status(struct cx18 *cx)
1035 	struct cx18_av_state *state = &cx->av_state;
1037 	u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
1038 	u8 gen_stat1 = cx18_av_read(cx, 0x40d);
1039 	u8 gen_stat2 = cx18_av_read(cx, 0x40e);
1065 static void log_audio_status(struct cx18 *cx)
1067 	struct cx18_av_state *state = &cx->av_state;
1069 	u8 download_ctl = cx18_av_read(cx, 0x803);
1070 	u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
1071 	u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
1072 	u8 audio_config = cx18_av_read(cx, 0x808);
1073 	u8 pref_mode = cx18_av_read(cx, 0x809);
1074 	u8 afc0 = cx18_av_read(cx, 0x80b);
1075 	u8 mute_ctl = cx18_av_read(cx, 0x8d3);
1216 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1217 	log_video_status(cx);
1218 	log_audio_status(cx);
1226 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1231 	reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
1238 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1242 	cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val);
1299 int cx18_av_probe(struct cx18 *cx)
1301 	struct cx18_av_state *state = &cx->av_state;
1305 	state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff;
1316 	v4l2_set_subdevdata(sd, cx);
1318 		 "%s %03x", cx->v4l2_dev.name, (state->rev >> 4));
1352 	err = v4l2_device_register_subdev(&cx->v4l2_dev, sd);
1356 		cx18_av_init(cx);