Lines Matching defs:output
12 // Slight changes for video timing and attachment output by
83 int output;
214 R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */
215 R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */
322 R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */
323 R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */
343 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
346 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */
463 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */
464 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */
465 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */
510 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
520 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
896 /* Set output width/height */
1287 u32 input, u32 output, u32 config)
1292 v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n",
1293 input, output);
1304 if (state->input == input && state->output == output)
1306 v4l2_dbg(1, debug, sd, "now setting %s input %s output\n",
1308 (output == SAA7115_IPORT_ON) ? "iport on" : "iport off");
1318 ((output & 0xc0) ^ 0x40));
1321 ((output & 2) ? 0x0a : 0));
1334 state->output = output;
1339 (state->output & 0x01));
1365 v4l2_dbg(1, debug, sd, "%s output\n",
1883 state->output = SAA7115_IPORT_ON;