Lines Matching refs:state
412 static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr)
414 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
425 if (state->error)
436 state->error = ret;
441 static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val)
444 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
447 if (state->error)
455 state->error = ret;
459 static u16 s5k5baf_read(struct s5k5baf *state, u16 addr)
461 s5k5baf_i2c_write(state, REG_CMDRD_ADDR, addr);
462 return s5k5baf_i2c_read(state, REG_CMD_BUF);
465 static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val)
467 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
468 s5k5baf_i2c_write(state, REG_CMD_BUF, val);
471 static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr,
474 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
477 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
478 if (state->error)
497 state->error = ret;
505 #define s5k5baf_write_seq(state, addr, seq...) \
506 s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \
520 static void s5k5baf_write_nseq(struct s5k5baf *state, const u16 *nseq)
528 s5k5baf_write_arr_seq(state, addr, count, nseq);
533 static void s5k5baf_synchronize(struct s5k5baf *state, int timeout, u16 addr)
538 s5k5baf_write(state, addr, 1);
540 reg = s5k5baf_read(state, addr);
541 if (state->error || !reg)
546 v4l2_err(&state->sd, "timeout on register synchronize (%#x)\n", addr);
547 state->error = -ETIMEDOUT;
550 static u16 *s5k5baf_fw_get_seq(struct s5k5baf *state, u16 seq_id)
552 struct s5k5baf_fw *fw = state->fw;
569 static void s5k5baf_hw_patch(struct s5k5baf *state)
571 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_PATCH);
574 s5k5baf_write_nseq(state, seq);
577 static void s5k5baf_hw_set_clocks(struct s5k5baf *state)
579 unsigned long mclk = state->mclk_frequency / 1000;
590 s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16);
591 s5k5baf_write_nseq(state, nseq_clk_cfg);
593 s5k5baf_synchronize(state, 250, REG_I_INIT_PARAMS_UPDATED);
594 status = s5k5baf_read(state, REG_I_ERROR_INFO);
595 if (!state->error && status) {
596 v4l2_err(&state->sd, "error configuring PLL (%d)\n", status);
597 state->error = -EINVAL;
602 static void s5k5baf_hw_set_ccm(struct s5k5baf *state)
604 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CCM);
607 s5k5baf_write_nseq(state, seq);
611 static void s5k5baf_hw_set_cis(struct s5k5baf *state)
613 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CIS);
618 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_HW);
619 s5k5baf_write_nseq(state, seq);
620 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
623 static void s5k5baf_hw_sync_cfg(struct s5k5baf *state)
625 s5k5baf_write(state, REG_G_PREV_CFG_CHG, 1);
626 if (state->apply_crop) {
627 s5k5baf_write(state, REG_G_INPUTS_CHANGE_REQ, 1);
628 s5k5baf_write(state, REG_G_PREV_CFG_BYPASS_CHANGED, 1);
630 s5k5baf_synchronize(state, 500, REG_G_NEW_CFG_SYNC);
633 static void s5k5baf_hw_set_mirror(struct s5k5baf *state)
635 u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1);
637 s5k5baf_write(state, REG_P_PREV_MIRROR(0), flip);
638 if (state->streaming)
639 s5k5baf_hw_sync_cfg(state);
642 static void s5k5baf_hw_set_alg(struct s5k5baf *state, u16 alg, bool enable)
646 if (!state->valid_auto_alg)
647 cur_alg = s5k5baf_read(state, REG_DBG_AUTOALG_EN);
649 cur_alg = state->auto_alg;
654 s5k5baf_write(state, REG_DBG_AUTOALG_EN, new_alg);
656 if (state->error)
659 state->valid_auto_alg = 1;
660 state->auto_alg = new_alg;
664 static void s5k5baf_hw_set_awb(struct s5k5baf *state, int awb)
666 struct s5k5baf_ctrls *ctrls = &state->ctrls;
669 s5k5baf_write_seq(state, REG_SF_RGAIN,
675 s5k5baf_hw_set_alg(state, AALG_WB_EN, awb);
679 static void s5k5baf_hw_set_user_exposure(struct s5k5baf *state, int exposure)
683 s5k5baf_write_seq(state, REG_SF_USR_EXPOSURE_L,
687 static void s5k5baf_hw_set_user_gain(struct s5k5baf *state, int gain)
689 s5k5baf_write_seq(state, REG_SF_USR_TOT_GAIN, gain, 1);
693 static void s5k5baf_hw_set_auto_exposure(struct s5k5baf *state, int value)
696 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, true);
698 unsigned int exp_time = state->ctrls.exposure->val;
700 s5k5baf_hw_set_user_exposure(state, exp_time);
701 s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val);
702 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, false);
706 static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v)
709 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, true);
713 s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1);
714 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, false);
718 static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val)
729 s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]);
747 static int s5k5baf_clear_error(struct s5k5baf *state)
749 int ret = state->error;
751 state->error = 0;
755 static int s5k5baf_hw_set_video_bus(struct s5k5baf *state)
759 if (state->bus_type == V4L2_MBUS_CSI2_DPHY)
764 s5k5baf_write_seq(state, REG_OIF_EN_MIPI_LANES,
765 state->nlanes, en_pkts, 1);
767 return s5k5baf_clear_error(state);
770 static u16 s5k5baf_get_cfg_error(struct s5k5baf *state)
772 u16 err = s5k5baf_read(state, REG_G_PREV_CFG_ERROR);
774 s5k5baf_write(state, REG_G_PREV_CFG_ERROR, 0);
778 static void s5k5baf_hw_set_fiv(struct s5k5baf *state, u16 fiv)
780 s5k5baf_write(state, REG_P_MAX_FR_TIME(0), fiv);
781 s5k5baf_hw_sync_cfg(state);
784 static void s5k5baf_hw_find_min_fiv(struct s5k5baf *state)
789 fiv = s5k5baf_read(state, REG_G_ACTUAL_P_FR_TIME);
790 if (state->error)
794 s5k5baf_hw_set_fiv(state, fiv);
795 err = s5k5baf_get_cfg_error(state);
796 if (state->error)
803 state->fiv = fiv;
804 v4l2_info(&state->sd,
808 v4l2_err(&state->sd,
810 state->error = -EINVAL;
813 v4l2_err(&state->sd, "cannot find correct frame interval\n");
814 state->error = -ERANGE;
817 static void s5k5baf_hw_validate_cfg(struct s5k5baf *state)
821 err = s5k5baf_get_cfg_error(state);
822 if (state->error)
827 state->apply_cfg = 1;
830 s5k5baf_hw_find_min_fiv(state);
831 if (!state->error)
832 state->apply_cfg = 1;
835 v4l2_err(&state->sd,
837 state->error = -EINVAL;
851 static int s5k5baf_hw_set_crop_rects(struct s5k5baf *state)
857 p = &state->crop_sink;
858 s5k5baf_write_seq(state, REG_G_PREVREQ_IN_WIDTH, p->width, p->height,
861 s5k5baf_rescale(&r, &state->crop_source, &state->crop_sink,
862 &state->compose);
863 s5k5baf_write_seq(state, REG_G_PREVZOOM_IN_WIDTH, r.width, r.height,
866 s5k5baf_synchronize(state, 500, REG_G_INPUTS_CHANGE_REQ);
867 s5k5baf_synchronize(state, 500, REG_G_PREV_CFG_BYPASS_CHANGED);
868 err = s5k5baf_get_cfg_error(state);
869 ret = s5k5baf_clear_error(state);
878 s5k5baf_hw_set_fiv(state, S5K5BAF_MAX_FR_TIME);
879 err = s5k5baf_get_cfg_error(state);
880 ret = s5k5baf_clear_error(state);
884 v4l2_err(&state->sd,
886 state->error = -EINVAL;
888 s5k5baf_hw_set_fiv(state, state->req_fiv);
889 s5k5baf_hw_validate_cfg(state);
892 v4l2_err(&state->sd, "crop error: %d\n", err);
896 if (!state->apply_cfg)
899 p = &state->crop_source;
900 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), p->width, p->height);
901 s5k5baf_hw_set_fiv(state, state->req_fiv);
902 s5k5baf_hw_validate_cfg(state);
904 return s5k5baf_clear_error(state);
907 static void s5k5baf_hw_set_config(struct s5k5baf *state)
909 u16 reg_fmt = s5k5baf_formats[state->pixfmt].reg_p_fmt;
910 struct v4l2_rect *r = &state->crop_source;
912 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0),
917 state->req_fiv, S5K5BAF_MIN_FR_TIME);
918 s5k5baf_hw_sync_cfg(state);
919 s5k5baf_hw_validate_cfg(state);
923 static void s5k5baf_hw_set_test_pattern(struct s5k5baf *state, int id)
925 s5k5baf_i2c_write(state, REG_PATTERN_WIDTH, 800);
926 s5k5baf_i2c_write(state, REG_PATTERN_HEIGHT, 511);
927 s5k5baf_i2c_write(state, REG_PATTERN_PARAM, 0);
928 s5k5baf_i2c_write(state, REG_PATTERN_SET, id);
931 static void s5k5baf_gpio_assert(struct s5k5baf *state, int id)
933 gpiod_set_value_cansleep(state->gpios[id], 1);
936 static void s5k5baf_gpio_deassert(struct s5k5baf *state, int id)
938 gpiod_set_value_cansleep(state->gpios[id], 0);
941 static int s5k5baf_power_on(struct s5k5baf *state)
945 ret = regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES, state->supplies);
949 ret = clk_set_rate(state->clock, state->mclk_frequency);
953 ret = clk_prepare_enable(state->clock);
957 v4l2_dbg(1, debug, &state->sd, "clock frequency: %ld\n",
958 clk_get_rate(state->clock));
960 s5k5baf_gpio_deassert(state, STBY);
962 s5k5baf_gpio_deassert(state, RSET);
966 regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, state->supplies);
968 v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret);
972 static int s5k5baf_power_off(struct s5k5baf *state)
976 state->streaming = 0;
977 state->apply_cfg = 0;
978 state->apply_crop = 0;
980 s5k5baf_gpio_assert(state, RSET);
981 s5k5baf_gpio_assert(state, STBY);
983 if (!IS_ERR(state->clock))
984 clk_disable_unprepare(state->clock);
987 state->supplies);
989 v4l2_err(&state->sd, "failed to disable regulators\n");
994 static void s5k5baf_hw_init(struct s5k5baf *state)
996 s5k5baf_i2c_write(state, AHB_MSB_ADDR_PTR, PAGE_IF_HW);
997 s5k5baf_i2c_write(state, REG_CLEAR_HOST_INT, 0);
998 s5k5baf_i2c_write(state, REG_SW_LOAD_COMPLETE, 1);
999 s5k5baf_i2c_write(state, REG_CMDRD_PAGE, PAGE_IF_SW);
1000 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
1007 static void s5k5baf_initialize_data(struct s5k5baf *state)
1009 state->pixfmt = 0;
1010 state->req_fiv = 10000 / 15;
1011 state->fiv = state->req_fiv;
1012 state->valid_auto_alg = 0;
1015 static int s5k5baf_load_setfile(struct s5k5baf *state)
1017 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1028 ret = s5k5baf_fw_parse(&c->dev, &state->fw, fw->size / 2,
1038 struct s5k5baf *state = to_s5k5baf(sd);
1041 mutex_lock(&state->lock);
1043 if (state->power != !on)
1047 if (state->fw == NULL)
1048 s5k5baf_load_setfile(state);
1050 s5k5baf_initialize_data(state);
1051 ret = s5k5baf_power_on(state);
1055 s5k5baf_hw_init(state);
1056 s5k5baf_hw_patch(state);
1057 s5k5baf_i2c_write(state, REG_SET_HOST_INT, 1);
1058 s5k5baf_hw_set_clocks(state);
1060 ret = s5k5baf_hw_set_video_bus(state);
1064 s5k5baf_hw_set_cis(state);
1065 s5k5baf_hw_set_ccm(state);
1067 ret = s5k5baf_clear_error(state);
1069 state->power++;
1071 s5k5baf_power_off(state);
1072 state->power--;
1076 mutex_unlock(&state->lock);
1079 ret = v4l2_ctrl_handler_setup(&state->ctrls.handler);
1084 static void s5k5baf_hw_set_stream(struct s5k5baf *state, int enable)
1086 s5k5baf_write_seq(state, REG_G_ENABLE_PREV, enable, 1);
1091 struct s5k5baf *state = to_s5k5baf(sd);
1094 mutex_lock(&state->lock);
1096 if (state->streaming == !!on) {
1102 s5k5baf_hw_set_config(state);
1103 ret = s5k5baf_hw_set_crop_rects(state);
1106 s5k5baf_hw_set_stream(state, 1);
1107 s5k5baf_i2c_write(state, 0xb0cc, 0x000b);
1109 s5k5baf_hw_set_stream(state, 0);
1111 ret = s5k5baf_clear_error(state);
1113 state->streaming = !state->streaming;
1116 mutex_unlock(&state->lock);
1125 struct s5k5baf *state = to_s5k5baf(sd);
1129 * subdev active state API.
1134 mutex_lock(&state->lock);
1135 fi->interval.numerator = state->fiv;
1137 mutex_unlock(&state->lock);
1142 static void __s5k5baf_set_frame_interval(struct s5k5baf *state,
1148 state->req_fiv = S5K5BAF_MAX_FR_TIME;
1150 state->req_fiv = clamp_t(u32,
1155 state->fiv = state->req_fiv;
1156 if (state->apply_cfg) {
1157 s5k5baf_hw_set_fiv(state, state->req_fiv);
1158 s5k5baf_hw_validate_cfg(state);
1160 *i = (struct v4l2_fract){ state->fiv, 10000 };
1161 if (state->fiv == state->req_fiv)
1162 v4l2_info(&state->sd, "frame interval changed to %d00us\n",
1163 state->fiv);
1170 struct s5k5baf *state = to_s5k5baf(sd);
1174 * subdev active state API.
1179 mutex_lock(&state->lock);
1180 __s5k5baf_set_frame_interval(state, fi);
1181 mutex_unlock(&state->lock);
1287 struct s5k5baf *state = to_s5k5baf(sd);
1303 mutex_lock(&state->lock);
1304 pixfmt = &s5k5baf_formats[state->pixfmt];
1305 mf->width = state->crop_source.width;
1306 mf->height = state->crop_source.height;
1309 mutex_unlock(&state->lock);
1319 struct s5k5baf *state = to_s5k5baf(sd);
1335 mutex_lock(&state->lock);
1337 if (state->streaming) {
1338 mutex_unlock(&state->lock);
1342 state->pixfmt = s5k5baf_try_isp_format(mf);
1343 pixfmt = &s5k5baf_formats[state->pixfmt];
1346 mf->width = state->crop_source.width;
1347 mf->height = state->crop_source.height;
1349 mutex_unlock(&state->lock);
1382 struct s5k5baf *state = to_s5k5baf(sd);
1406 mutex_lock(&state->lock);
1409 sel->r = state->crop_sink;
1412 sel->r = state->compose;
1415 sel->r = state->crop_source;
1424 mutex_unlock(&state->lock);
1475 struct s5k5baf *state = to_s5k5baf(sd);
1502 &state->crop_sink,
1503 &state->compose,
1504 &state->crop_source
1506 mutex_lock(&state->lock);
1507 if (state->streaming) {
1510 if (sel->r.width < state->crop_source.width)
1511 sel->r.width = state->crop_source.width;
1512 if (sel->r.height < state->crop_source.height)
1513 sel->r.height = state->crop_source.height;
1515 sel->r.width = state->crop_source.width;
1516 sel->r.height = state->crop_source.height;
1520 if (!s5k5baf_cmp_rect(&state->crop_sink, &s5k5baf_cis_rect) ||
1521 !s5k5baf_cmp_rect(&state->compose, &s5k5baf_cis_rect))
1522 state->apply_crop = 1;
1523 if (state->streaming)
1524 ret = s5k5baf_hw_set_crop_rects(state);
1525 mutex_unlock(&state->lock);
1560 struct s5k5baf *state = to_s5k5baf(sd);
1565 mutex_lock(&state->lock);
1567 if (state->power == 0)
1572 s5k5baf_hw_set_awb(state, ctrl->val);
1576 s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val);
1580 s5k5baf_hw_set_colorfx(state, ctrl->val);
1584 s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val);
1588 s5k5baf_hw_set_auto_exposure(state, ctrl->val);
1592 s5k5baf_hw_set_mirror(state);
1596 s5k5baf_hw_set_anti_flicker(state, ctrl->val);
1600 s5k5baf_write(state, REG_USER_SATURATION, ctrl->val);
1604 s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val);
1608 s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val);
1609 if (state->apply_cfg)
1610 s5k5baf_hw_sync_cfg(state);
1614 s5k5baf_hw_set_test_pattern(state, ctrl->val);
1618 ret = s5k5baf_clear_error(state);
1619 mutex_unlock(&state->lock);
1637 static int s5k5baf_initialize_ctrls(struct s5k5baf *state)
1640 struct s5k5baf_ctrls *ctrls = &state->ctrls;
1646 v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret);
1694 v4l2_err(&state->sd, "error creating controls (%d)\n",
1701 state->sd.ctrl_handler = hdl;
1712 mf = v4l2_subdev_state_get_format(fh->state, PAD_CIS);
1718 mf = v4l2_subdev_state_get_format(fh->state, PAD_OUT);
1725 *v4l2_subdev_state_get_crop(fh->state, PAD_CIS) = s5k5baf_cis_rect;
1726 *v4l2_subdev_state_get_compose(fh->state, PAD_CIS) = s5k5baf_cis_rect;
1727 *v4l2_subdev_state_get_crop(fh->state, PAD_OUT) = s5k5baf_cis_rect;
1732 static int s5k5baf_check_fw_revision(struct s5k5baf *state)
1737 api_ver = s5k5baf_read(state, REG_FW_APIVER);
1738 fw_rev = s5k5baf_read(state, REG_FW_REVISION) & 0xff;
1739 s_id = s5k5baf_read(state, REG_FW_SENSOR_ID);
1740 ret = s5k5baf_clear_error(state);
1744 v4l2_info(&state->sd, "FW API=%#x, revision=%#x sensor_id=%#x\n",
1748 v4l2_err(&state->sd, "FW API version not supported\n");
1757 struct s5k5baf *state = to_s5k5baf(sd);
1760 ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->cis_sd);
1763 state->cis_sd.name);
1765 ret = media_create_pad_link(&state->cis_sd.entity, PAD_CIS,
1766 &state->sd.entity, PAD_CIS,
1774 struct s5k5baf *state = to_s5k5baf(sd);
1775 v4l2_device_unregister_subdev(&state->cis_sd);
1803 static int s5k5baf_configure_gpios(struct s5k5baf *state)
1807 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1827 state->gpios[i] = gpio;
1832 static int s5k5baf_parse_device_node(struct s5k5baf *state, struct device *dev)
1845 &state->mclk_frequency);
1847 state->mclk_frequency = S5K5BAF_DEFAULT_MCLK_FREQ;
1849 state->mclk_frequency);
1863 state->bus_type = ep.bus_type;
1865 switch (state->bus_type) {
1867 state->nlanes = ep.bus.mipi_csi2.num_data_lanes;
1880 static int s5k5baf_configure_subdevs(struct s5k5baf *state,
1886 sd = &state->cis_sd;
1889 v4l2_set_subdevdata(sd, state);
1896 state->cis_pad.flags = MEDIA_PAD_FL_SOURCE;
1898 ret = media_entity_pads_init(&sd->entity, NUM_CIS_PADS, &state->cis_pad);
1902 sd = &state->sd;
1910 state->pads[PAD_CIS].flags = MEDIA_PAD_FL_SINK;
1911 state->pads[PAD_OUT].flags = MEDIA_PAD_FL_SOURCE;
1913 ret = media_entity_pads_init(&sd->entity, NUM_ISP_PADS, state->pads);
1918 media_entity_cleanup(&state->cis_sd.entity);
1924 static int s5k5baf_configure_regulators(struct s5k5baf *state)
1926 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1931 state->supplies[i].supply = s5k5baf_supply_names[i];
1934 state->supplies);
1942 struct s5k5baf *state;
1945 state = devm_kzalloc(&c->dev, sizeof(*state), GFP_KERNEL);
1946 if (!state)
1949 mutex_init(&state->lock);
1950 state->crop_sink = s5k5baf_cis_rect;
1951 state->compose = s5k5baf_cis_rect;
1952 state->crop_source = s5k5baf_cis_rect;
1954 ret = s5k5baf_parse_device_node(state, &c->dev);
1958 ret = s5k5baf_configure_subdevs(state, c);
1962 ret = s5k5baf_configure_gpios(state);
1966 ret = s5k5baf_configure_regulators(state);
1970 state->clock = devm_clk_get(state->sd.dev, S5K5BAF_CLK_NAME);
1971 if (IS_ERR(state->clock)) {
1976 ret = s5k5baf_power_on(state);
1981 s5k5baf_hw_init(state);
1982 ret = s5k5baf_check_fw_revision(state);
1984 s5k5baf_power_off(state);
1988 ret = s5k5baf_initialize_ctrls(state);
1992 ret = v4l2_async_register_subdev(&state->sd);
1999 v4l2_ctrl_handler_free(state->sd.ctrl_handler);
2001 media_entity_cleanup(&state->sd.entity);
2002 media_entity_cleanup(&state->cis_sd.entity);
2009 struct s5k5baf *state = to_s5k5baf(sd);
2015 sd = &state->cis_sd;