Lines Matching defs:ov64a40
2832 struct ov64a40 {
2859 static inline struct ov64a40 *sd_to_ov64a40(struct v4l2_subdev *sd)
2861 return container_of_const(sd, struct ov64a40, sd);
2865 ov64a40_get_timings(struct ov64a40 *ov64a40, unsigned int link_freq_index)
2867 s64 link_freq = ov64a40->link_frequencies[link_freq_index];
2872 return &ov64a40->mode->timings_default[timings_index];
2875 static int ov64a40_program_geometry(struct ov64a40 *ov64a40)
2877 struct ov64a40_mode *mode = ov64a40->mode;
2884 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL0,
2886 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL2,
2888 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL4,
2890 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL6,
2894 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL10,
2896 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL12,
2898 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL8,
2900 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLA,
2904 timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val);
2905 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLC, timings->ppl, &ret);
2906 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLE, timings->vts, &ret);
2911 static int ov64a40_program_subsampling(struct ov64a40 *ov64a40)
2913 struct ov64a40_subsampling *subsampling = &ov64a40->mode->subsampling;
2917 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL14,
2920 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL15,
2925 cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20,
2929 cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21,
2937 static int ov64a40_start_streaming(struct ov64a40 *ov64a40,
2940 const struct ov64a40_reglist *reglist = &ov64a40->mode->reglist;
2945 ret = pm_runtime_resume_and_get(ov64a40->dev);
2949 ret = cci_multi_reg_write(ov64a40->cci, ov64a40_init,
2954 ret = cci_multi_reg_write(ov64a40->cci, reglist->regvals,
2959 ret = ov64a40_program_geometry(ov64a40);
2963 ret = ov64a40_program_subsampling(ov64a40);
2967 ret = __v4l2_ctrl_handler_setup(&ov64a40->ctrl_handler);
2971 ret = cci_write(ov64a40->cci, OV64A40_REG_SMIA,
2977 __v4l2_ctrl_grab(ov64a40->link_freq, true);
2978 __v4l2_ctrl_grab(ov64a40->vflip, true);
2979 __v4l2_ctrl_grab(ov64a40->hflip, true);
2982 timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val);
2987 delay += DIV_ROUND_UP(timings->ppl * 4 * ov64a40->exposure->cur.val,
2994 pm_runtime_mark_last_busy(ov64a40->dev);
2995 pm_runtime_put_autosuspend(ov64a40->dev);
3000 static int ov64a40_stop_streaming(struct ov64a40 *ov64a40,
3003 cci_update_bits(ov64a40->cci, OV64A40_REG_SMIA, BIT(0), 0, NULL);
3004 pm_runtime_mark_last_busy(ov64a40->dev);
3005 pm_runtime_put_autosuspend(ov64a40->dev);
3007 __v4l2_ctrl_grab(ov64a40->link_freq, false);
3008 __v4l2_ctrl_grab(ov64a40->vflip, false);
3009 __v4l2_ctrl_grab(ov64a40->hflip, false);
3016 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3022 ret = ov64a40_start_streaming(ov64a40, state);
3024 ret = ov64a40_stop_streaming(ov64a40, state);
3034 static u32 ov64a40_mbus_code(struct ov64a40 *ov64a40)
3036 unsigned int index = ov64a40->hflip->val << 1 | ov64a40->vflip->val;
3041 static void ov64a40_update_pad_fmt(struct ov64a40 *ov64a40,
3045 fmt->code = ov64a40_mbus_code(ov64a40);
3058 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3063 ov64a40_update_pad_fmt(ov64a40, &ov64a40_modes[0], format);
3078 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3083 code->code = ov64a40_mbus_code(ov64a40);
3092 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3099 code = ov64a40_mbus_code(ov64a40);
3147 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3156 ov64a40_update_pad_fmt(ov64a40, mode, &fmt->format);
3159 if (ov64a40->mode == mode && format->code == fmt->format.code)
3168 ov64a40->mode = mode;
3172 timings = ov64a40_get_timings(ov64a40,
3173 ov64a40->link_freq->cur.val);
3176 __v4l2_ctrl_modify_range(ov64a40->vblank, OV64A40_VBLANK_MIN,
3178 __v4l2_ctrl_s_ctrl(ov64a40->vblank, vblank_def);
3181 __v4l2_ctrl_modify_range(ov64a40->exposure,
3186 __v4l2_ctrl_modify_range(ov64a40->hblank,
3221 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3224 ret = clk_prepare_enable(ov64a40->xclk);
3229 ov64a40->supplies);
3231 clk_disable_unprepare(ov64a40->xclk);
3236 gpiod_set_value_cansleep(ov64a40->reset_gpio, 0);
3246 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3248 gpiod_set_value_cansleep(ov64a40->reset_gpio, 1);
3250 ov64a40->supplies);
3251 clk_disable_unprepare(ov64a40->xclk);
3256 static int ov64a40_link_freq_config(struct ov64a40 *ov64a40, int link_freq_id)
3262 cci_multi_reg_write(ov64a40->cci, ov64a40_pll_config,
3266 link_frequency = ov64a40->link_frequencies[link_freq_id];
3268 cci_write(ov64a40->cci, OV64A40_PLL1_MULTIPLIER, 0x0078, &ret);
3275 struct ov64a40 *ov64a40 = container_of(ctrl->handler, struct ov64a40,
3281 int exp_max = ov64a40->mode->height + ctrl->val
3283 int exp_val = min(ov64a40->exposure->cur.val, exp_max);
3285 __v4l2_ctrl_modify_range(ov64a40->exposure,
3286 ov64a40->exposure->minimum,
3290 pm_status = pm_runtime_get_if_active(ov64a40->dev);
3296 ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_EXPO,
3300 ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_GAIN,
3304 int vts = ctrl->val + ov64a40->mode->height;
3306 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_LOW, vts, &ret);
3307 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_MID,
3309 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_HIGH,
3314 ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20,
3320 ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21,
3327 ret = cci_write(ov64a40->cci, OV64A40_REG_TEST_PATTERN,
3331 ret = ov64a40_link_freq_config(ov64a40, ctrl->val);
3334 dev_err(ov64a40->dev, "Unhandled control: %#x\n", ctrl->id);
3340 pm_runtime_mark_last_busy(ov64a40->dev);
3341 pm_runtime_put_autosuspend(ov64a40->dev);
3351 static int ov64a40_init_controls(struct ov64a40 *ov64a40)
3354 struct v4l2_ctrl_handler *hdlr = &ov64a40->ctrl_handler;
3367 ov64a40->link_freq =
3370 ov64a40->num_link_frequencies - 1,
3371 0, ov64a40->link_frequencies);
3378 timings = ov64a40_get_timings(ov64a40, 0);
3380 ov64a40->exposure = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3385 hblank_val = timings->ppl * 4 - ov64a40->mode->width;
3386 ov64a40->hblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3389 if (ov64a40->hblank)
3390 ov64a40->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
3392 vblank_def = timings->vts - ov64a40->mode->height;
3393 vblank_max = OV64A40_VTS_MAX - ov64a40->mode->height;
3394 ov64a40->vblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3402 ov64a40->hflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3404 if (ov64a40->hflip)
3405 ov64a40->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
3407 ov64a40->vflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3409 if (ov64a40->vflip)
3410 ov64a40->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
3414 dev_err(ov64a40->dev, "control init failed: %d\n", ret);
3418 ret = v4l2_fwnode_device_parse(ov64a40->dev, &props);
3427 ov64a40->sd.ctrl_handler = hdlr;
3436 static int ov64a40_identify(struct ov64a40 *ov64a40)
3441 ret = cci_read(ov64a40->cci, OV64A40_REG_CHIP_ID, &id, NULL);
3443 dev_err(ov64a40->dev, "Failed to read chip id: %d\n", ret);
3448 dev_err(ov64a40->dev, "chip id mismatch: %#llx\n", id);
3452 dev_dbg(ov64a40->dev, "OV64A40 chip identified: %#llx\n", id);
3457 static int ov64a40_parse_dt(struct ov64a40 *ov64a40)
3466 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(ov64a40->dev),
3469 dev_err(ov64a40->dev, "Failed to find endpoint\n");
3476 dev_err(ov64a40->dev, "Failed to parse endpoint\n");
3481 dev_err(ov64a40->dev, "Unsupported number of data lanes: %u\n",
3488 dev_warn(ov64a40->dev, "no link frequencies defined\n");
3494 dev_warn(ov64a40->dev,
3500 ov64a40->link_frequencies =
3501 devm_kcalloc(ov64a40->dev, v4l2_fwnode.nr_of_link_frequencies,
3504 if (!ov64a40->link_frequencies) {
3508 ov64a40->num_link_frequencies = v4l2_fwnode.nr_of_link_frequencies;
3513 dev_err(ov64a40->dev,
3520 ov64a40->link_frequencies[i] = v4l2_fwnode.link_frequencies[i];
3528 static int ov64a40_get_regulators(struct ov64a40 *ov64a40)
3530 struct i2c_client *client = v4l2_get_subdevdata(&ov64a40->sd);
3534 ov64a40->supplies[i].supply = ov64a40_supply_names[i];
3538 ov64a40->supplies);
3543 struct ov64a40 *ov64a40;
3547 ov64a40 = devm_kzalloc(&client->dev, sizeof(*ov64a40), GFP_KERNEL);
3548 if (!ov64a40)
3551 ov64a40->dev = &client->dev;
3552 v4l2_i2c_subdev_init(&ov64a40->sd, client, &ov64a40_subdev_ops);
3554 ov64a40->cci = devm_cci_regmap_init_i2c(client, 16);
3555 if (IS_ERR(ov64a40->cci)) {
3557 return PTR_ERR(ov64a40->cci);
3560 ov64a40->xclk = devm_clk_get(&client->dev, NULL);
3561 if (IS_ERR(ov64a40->xclk))
3562 return dev_err_probe(&client->dev, PTR_ERR(ov64a40->xclk),
3565 xclk_freq = clk_get_rate(ov64a40->xclk);
3572 ret = ov64a40_get_regulators(ov64a40);
3576 ov64a40->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3578 if (IS_ERR(ov64a40->reset_gpio))
3579 return dev_err_probe(&client->dev, PTR_ERR(ov64a40->reset_gpio),
3582 ret = ov64a40_parse_dt(ov64a40);
3590 ret = ov64a40_identify(ov64a40);
3594 ov64a40->mode = &ov64a40_modes[0];
3602 ret = ov64a40_init_controls(ov64a40);
3607 ov64a40->sd.internal_ops = &ov64a40_internal_ops;
3608 ov64a40->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE
3610 ov64a40->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
3612 ov64a40->pad.flags = MEDIA_PAD_FL_SOURCE;
3613 ret = media_entity_pads_init(&ov64a40->sd.entity, 1, &ov64a40->pad);
3619 ov64a40->sd.state_lock = ov64a40->ctrl_handler.lock;
3620 ret = v4l2_subdev_init_finalize(&ov64a40->sd);
3626 ret = v4l2_async_register_subdev_sensor(&ov64a40->sd);
3639 v4l2_subdev_cleanup(&ov64a40->sd);
3641 media_entity_cleanup(&ov64a40->sd.entity);
3643 v4l2_ctrl_handler_free(ov64a40->sd.ctrl_handler);
3667 { .compatible = "ovti,ov64a40" },
3678 .name = "ov64a40",