Lines Matching refs:sysdiv
1378 u8 sysdiv)
1386 return sysclk / sysdiv;
1392 u8 *sysdiv)
1419 * increase sysdiv.
1443 *sysdiv = best_sysdiv;
1457 u8 prediv, mult, sysdiv;
1480 ov5640_calc_sys_clk(sensor, sysclk, &prediv, &mult, &sysdiv);
1529 (sysdiv << 4) | mipi_div);
1564 u8 *pll_prediv, u8 *pll_mult, u8 *sysdiv,
1571 sysdiv);
1581 u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div;
1589 ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv,
1601 * We need to set sysdiv according to the clock, and to clear
1605 0xff, sysdiv << 4);
1862 u32 multiplier, prediv, VCO, sysdiv, pll_rdiv;
1878 sysdiv = temp1 >> 4;
1879 if (sysdiv == 0)
1880 sysdiv = 16;
1899 if (!prediv || !sysdiv || !pll_rdiv || !bit_div2x)
1904 sysclk = VCO / sysdiv / pll_rdiv * 2 / bit_div2x / sclk_rdiv;