Lines Matching defs:ov2740
514 struct ov2740 {
544 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
546 return container_of(subdev, struct ov2740, sd);
558 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
560 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
588 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
590 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
607 static int ov2740_write_reg_list(struct ov2740 *ov2740,
610 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
615 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
628 static int ov2740_identify_module(struct ov2740 *ov2740)
630 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
634 if (ov2740->identified)
637 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
647 ov2740->identified = true;
652 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
656 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
661 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
665 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
669 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
673 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
678 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
683 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
689 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
694 struct ov2740 *ov2740 = container_of(ctrl->handler,
695 struct ov2740, ctrl_handler);
696 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
703 exposure_max = ov2740->cur_mode->height + ctrl->val -
705 __v4l2_ctrl_modify_range(ov2740->exposure,
706 ov2740->exposure->minimum,
707 exposure_max, ov2740->exposure->step,
717 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
722 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
727 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
732 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
733 ov2740->cur_mode->height + ctrl->val);
737 ret = ov2740_test_pattern(ov2740, ctrl->val);
754 static int ov2740_init_controls(struct ov2740 *ov2740)
763 ctrl_hdlr = &ov2740->ctrl_handler;
768 cur_mode = ov2740->cur_mode;
771 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
775 if (ov2740->link_freq)
776 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
779 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
786 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
791 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
794 if (ov2740->hblank)
795 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
804 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
818 ov2740->sd.ctrl_handler = ctrl_hdlr;
835 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
847 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
853 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
860 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
868 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
875 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
895 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
902 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
908 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
922 static int ov2740_start_streaming(struct ov2740 *ov2740)
924 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
929 ret = ov2740_identify_module(ov2740);
933 if (ov2740->nvm)
934 ov2740_load_otp_data(ov2740->nvm);
937 ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01);
945 link_freq_index = ov2740->cur_mode->link_freq_index;
947 ret = ov2740_write_reg_list(ov2740, reg_list);
953 reg_list = &ov2740->cur_mode->reg_list;
954 ret = ov2740_write_reg_list(ov2740, reg_list);
960 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
964 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
972 static void ov2740_stop_streaming(struct ov2740 *ov2740)
974 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
976 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
983 struct ov2740 *ov2740 = to_ov2740(sd);
988 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd);
995 ret = ov2740_start_streaming(ov2740);
998 ov2740_stop_streaming(ov2740);
1002 ov2740_stop_streaming(ov2740);
1016 struct ov2740 *ov2740 = to_ov2740(sd);
1020 mode = v4l2_find_nearest_size(ov2740->supported_modes,
1021 ov2740->supported_modes_count,
1031 ov2740->cur_mode = mode;
1032 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
1033 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
1038 __v4l2_ctrl_modify_range(ov2740->vblank,
1041 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
1043 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, h_blank);
1064 struct ov2740 *ov2740 = to_ov2740(sd);
1065 const struct ov2740_mode *supported_modes = ov2740->supported_modes;
1067 if (fse->index >= ov2740->supported_modes_count)
1084 struct ov2740 *ov2740 = to_ov2740(sd);
1086 ov2740_update_pad_format(&ov2740->supported_modes[0],
1118 struct ov2740 *ov2740 = to_ov2740(sd);
1179 ov2740->supported_modes = supported_modes_360mhz;
1180 ov2740->supported_modes_count =
1184 ov2740->supported_modes = supported_modes_180mhz;
1185 ov2740->supported_modes_count =
1193 if (!ov2740->supported_modes)
1219 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
1224 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd);
1247 struct ov2740 *ov2740)
1286 ov2740->nvm = nvm;
1293 struct ov2740 *ov2740 = to_ov2740(sd);
1295 gpiod_set_value_cansleep(ov2740->reset_gpio, 1);
1296 clk_disable_unprepare(ov2740->clk);
1303 struct ov2740 *ov2740 = to_ov2740(sd);
1306 ret = clk_prepare_enable(ov2740->clk);
1310 gpiod_set_value_cansleep(ov2740->reset_gpio, 0);
1319 struct ov2740 *ov2740;
1323 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1324 if (!ov2740)
1327 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1328 ov2740->sd.internal_ops = &ov2740_internal_ops;
1334 ov2740->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1335 if (IS_ERR(ov2740->reset_gpio))
1336 return dev_err_probe(dev, PTR_ERR(ov2740->reset_gpio),
1339 ov2740->clk = devm_clk_get_optional(dev, "clk");
1340 if (IS_ERR(ov2740->clk))
1341 return dev_err_probe(dev, PTR_ERR(ov2740->clk),
1351 ret = ov2740_identify_module(ov2740);
1358 ov2740->cur_mode = &ov2740->supported_modes[0];
1359 ret = ov2740_init_controls(ov2740);
1365 ov2740->sd.state_lock = ov2740->ctrl_handler.lock;
1366 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1367 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1368 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1369 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1370 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1376 ret = v4l2_subdev_init_finalize(&ov2740->sd);
1386 ret = v4l2_async_register_subdev_sensor(&ov2740->sd);
1392 ret = ov2740_register_nvmem(client, ov2740);
1399 v4l2_subdev_cleanup(&ov2740->sd);
1402 media_entity_cleanup(&ov2740->sd.entity);
1407 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1428 .name = "ov2740",