i2c/cx25840/cx25840-ir.c

124  * Note the largest clock divider value of 0xffff corresponds to:
145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
147 	return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
150 static inline unsigned int clock_divider_to_freq(unsigned int divider,
154 				 (divider + 1) * rollovers);
195 static u32 clock_divider_to_resolution(u16 divider)
202 	return DIV_ROUND_CLOSEST((1 << 2)  * ((u32) divider + 1) * 1000,
206 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
215 	n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
224 static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
235 	d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
248 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
257 	n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */
268  * significant part and (up to) 16 bit clock divider count as a modulus.
269  * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
393 				       u16 *divider)
395 	*divider = carrier_freq_to_clock_divider(freq);
396 	cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
397 	return clock_divider_to_carrier_freq(*divider);
402 				       u16 *divider)
404 	*divider = carrier_freq_to_clock_divider(freq);
405 	cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
406 	return clock_divider_to_carrier_freq(*divider);
410 				      u16 *divider)
417 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);
418 	cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
419 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
423 				      u16 *divider)
430 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);
431 	cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
432 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
633 	u16 divider;
642 	divider = (u16) atomic_read(&ir_state->rxclk_divider);
671 				  (u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000;