media/i2c/adv7842.c

457 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
466 	return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
929 		afe_write(sd, reg->reg & 0xff, val);
1292 		afe_write(sd, 0xc8, ctrl->val);
1795 		afe_write(sd, 0x00, 0x00); /* power up ADC */
1796 		afe_write(sd, 0xc8, 0x00); /* phase control */
1804 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1805 			afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1807 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1808 			afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1810 		afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1811 		afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1843 		afe_write(sd, 0x00, 0x00); /* power up ADC */
1844 		afe_write(sd, 0xc8, 0x00); /* phase control */
1856 		afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1857 		afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1908 		afe_write(sd, 0x00, 0xff); /* power down ADC */
1909 		afe_write(sd, 0xc8, 0x40); /* phase control */
1920 		afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1921 		afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
3036 	afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
3038 	afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3114 	afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */
3115 	afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */
3116 	afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */
3117 	afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */
3118 	afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */
3119 	afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */