Lines Matching refs:state
132 static int write_reg(struct stv *state, u16 reg, u8 val)
134 struct i2c_adapter *adap = state->base->i2c;
136 struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
141 state->base->adr, reg, val);
164 static int read_reg(struct stv *state, u16 reg, u8 *val)
166 return i2c_read_regs16(state->base->i2c, state->base->adr,
170 static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
172 return i2c_read_regs16(state->base->i2c, state->base->adr,
176 static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
181 mutex_lock(&state->base->reg_lock);
182 status = read_reg(state, reg, &tmp);
184 status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
185 mutex_unlock(&state->base->reg_lock);
189 static int write_field(struct stv *state, u32 field, u8 val)
194 status = read_reg(state, field >> 16, &old);
202 return write_reg(state, field >> 16, new);
206 write_field(state, state->nr ? FSTV0910_P2_##_reg : \
210 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
214 read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
433 static u8 get_optim_cloop(struct stv *state,
443 if (state->symbol_rate <= 3000000)
445 else if (state->symbol_rate <= 7000000)
447 else if (state->symbol_rate <= 15000000)
449 else if (state->symbol_rate <= 25000000)
460 static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
474 if (!state->started)
477 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
478 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
479 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
480 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
481 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
482 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
483 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
493 symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
501 static int get_signal_parameters(struct stv *state)
505 if (!state->started)
508 if (state->receive_mode == RCVMODE_DVBS2) {
509 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
510 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
511 state->pilots = (tmp & 0x01) != 0;
512 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
514 } else if (state->receive_mode == RCVMODE_DVBS) {
515 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
516 state->puncture_rate = FEC_NONE;
519 state->puncture_rate = FEC_1_2;
522 state->puncture_rate = FEC_2_3;
525 state->puncture_rate = FEC_3_4;
528 state->puncture_rate = FEC_5_6;
531 state->puncture_rate = FEC_7_8;
534 state->is_vcm = 0;
535 state->is_standard_broadcast = 1;
536 state->feroll_off = FE_SAT_35;
541 static int tracking_optimization(struct stv *state)
545 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
548 switch (state->receive_mode) {
559 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
561 if (state->receive_mode == RCVMODE_DVBS2) {
563 write_shared_reg(state,
564 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
567 if (state->fectype == DVBS2_64K) {
568 u8 aclc = get_optim_cloop(state, state->mod_cod,
569 state->pilots);
571 if (state->mod_cod <= FE_QPSK_910) {
572 write_reg(state, RSTV0910_P2_ACLC2S2Q +
573 state->regoff, aclc);
574 } else if (state->mod_cod <= FE_8PSK_910) {
575 write_reg(state, RSTV0910_P2_ACLC2S2Q +
576 state->regoff, 0x2a);
577 write_reg(state, RSTV0910_P2_ACLC2S28 +
578 state->regoff, aclc);
579 } else if (state->mod_cod <= FE_16APSK_910) {
580 write_reg(state, RSTV0910_P2_ACLC2S2Q +
581 state->regoff, 0x2a);
582 write_reg(state, RSTV0910_P2_ACLC2S216A +
583 state->regoff, aclc);
584 } else if (state->mod_cod <= FE_32APSK_910) {
585 write_reg(state, RSTV0910_P2_ACLC2S2Q +
586 state->regoff, 0x2a);
587 write_reg(state, RSTV0910_P2_ACLC2S232A +
588 state->regoff, aclc);
631 static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
641 if (!state->started)
644 if (state->receive_mode == RCVMODE_DVBS2) {
645 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
647 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
652 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
654 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
664 static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
669 int status = read_regs(state,
670 RSTV0910_P2_ERRCNT12 + state->regoff,
677 state->last_berdenominator = 1ULL << ((state->berscale * 2) +
679 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
681 if (state->last_bernumerator < 256 && state->berscale < 6) {
682 state->berscale += 1;
683 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
684 state->regoff,
685 0x20 | state->berscale);
686 } else if (state->last_bernumerator > 1024 &&
687 state->berscale > 2) {
688 state->berscale -= 1;
689 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
690 state->regoff, 0x20 |
691 state->berscale);
694 *bernumerator = state->last_bernumerator;
695 *berdenominator = state->last_berdenominator;
739 static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
744 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
751 state->last_berdenominator =
752 dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
753 state->fectype) <<
754 (state->berscale * 2);
755 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
757 if (state->last_bernumerator < 256 && state->berscale < 6) {
758 state->berscale += 1;
759 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
760 0x20 | state->berscale);
761 } else if (state->last_bernumerator > 1024 &&
762 state->berscale > 2) {
763 state->berscale -= 1;
764 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
765 0x20 | state->berscale);
768 *bernumerator = state->last_bernumerator;
769 *berdenominator = state->last_berdenominator;
773 static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
779 switch (state->receive_mode) {
781 return get_bit_error_rate_s(state,
784 return get_bit_error_rate_s2(state,
792 static int set_mclock(struct stv *state, u32 master_clock)
796 u32 quartz = state->base->extclk / 1000000;
845 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
846 write_reg(state, RSTV0910_NCOARSE2, odf);
847 write_reg(state, RSTV0910_NCOARSE1, ndiv);
850 state->base->mclk = fvco / (2 * odf) * 1000000;
855 static int stop(struct stv *state)
857 if (state->started) {
860 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
861 state->tscfgh | 0x01);
862 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
864 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
866 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
868 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
869 state->started = 0;
871 state->receive_mode = RCVMODE_NONE;
875 static void set_pls(struct stv *state, u32 pls_code)
877 if (pls_code == state->cur_scrambling_code)
881 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
883 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
885 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
887 state->cur_scrambling_code = pls_code;
890 static void set_isi(struct stv *state, u32 isi)
899 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
901 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
907 static void set_stream_modes(struct stv *state,
910 set_isi(state, p->stream_id);
911 set_pls(state, p->scrambling_sequence_index);
914 static int init_search_param(struct stv *state,
928 set_stream_modes(state, p);
932 static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
958 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
961 static int set_vth_default(struct stv *state)
963 state->vth[0] = 0xd7;
964 state->vth[1] = 0x85;
965 state->vth[2] = 0x58;
966 state->vth[3] = 0x3a;
967 state->vth[4] = 0x34;
968 state->vth[5] = 0x28;
969 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
970 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
971 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
972 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
973 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
974 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
978 static int set_vth(struct stv *state)
990 int status = read_regs(state,
991 RSTV0910_P2_NNOSDATAT1 + state->regoff,
998 if (state->vth[i] > vth)
999 state->vth[i] = vth;
1001 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
1002 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
1003 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
1004 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
1005 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
1006 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1010 static int start(struct stv *state, struct dtv_frontend_properties *p)
1019 state->receive_mode = RCVMODE_NONE;
1020 state->demod_lock_time = 0;
1023 if (state->started)
1024 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
1026 init_search_param(state, p);
1029 state->demod_timeout = 3000;
1030 state->fec_timeout = 2000;
1032 state->demod_timeout = 2500;
1033 state->fec_timeout = 1300;
1035 state->demod_timeout = 1000;
1036 state->fec_timeout = 650;
1038 state->demod_timeout = 700;
1039 state->fec_timeout = 350;
1041 state->demod_timeout = 400;
1042 state->fec_timeout = 200;
1044 state->demod_timeout = 300;
1045 state->fec_timeout = 200;
1049 symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
1050 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1052 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1054 state->demod_bits |= 0x80;
1055 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1058 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd);
1059 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1062 write_shared_reg(state,
1063 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
1066 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);
1067 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1069 enable_puncture_rate(state, FEC_NONE);
1072 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1073 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1074 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1075 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1076 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1077 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1079 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1080 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1081 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1082 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1088 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1089 write_reg(state, RSTV0910_TSTRES0, 0);
1091 set_vth_default(state);
1093 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1095 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1098 freq = (state->search_range / 2000) + 80;
1100 freq = (state->search_range / 2000) + 1600;
1101 freq = (freq << 16) / (state->base->mclk / 1000);
1103 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1105 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
1108 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1110 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1113 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1114 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1116 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1118 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1120 state->demod_lock_time += TUNING_DELAY;
1121 state->started = 1;
1126 static int init_diseqc(struct stv *state)
1128 u16 offs = state->nr ? 0x40 : 0; /* Address offset */
1129 u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
1132 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1133 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1134 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1135 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1139 static int probe(struct stv *state)
1143 state->receive_mode = RCVMODE_NONE;
1144 state->started = 0;
1146 if (read_reg(state, RSTV0910_MID, &id) < 0)
1153 write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1155 write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1157 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1159 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */
1160 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */
1161 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
1162 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1163 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
1165 if (state->single)
1166 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
1168 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
1170 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1171 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
1173 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1174 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1175 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1176 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1178 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1179 write_reg(state, RSTV0910_TSTRES0, 0x00);
1181 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1182 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1184 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1185 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1187 set_mclock(state, 135000000);
1190 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1191 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1192 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
1193 write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1195 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1197 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1198 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1199 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
1200 write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1202 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1205 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1206 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1207 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1208 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1210 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1211 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1213 write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
1214 write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
1216 write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
1217 write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
1219 init_diseqc(state);
1225 struct stv *state = fe->demodulator_priv;
1226 u8 i2crpt = state->i2crpt & ~0x86;
1239 mutex_lock(&state->base->i2c_lock);
1245 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
1248 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1249 mutex_unlock(&state->base->i2c_lock);
1250 dev_err(&state->base->i2c->dev,
1256 state->i2crpt = i2crpt;
1259 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1260 mutex_unlock(&state->base->i2c_lock);
1266 struct stv *state = fe->demodulator_priv;
1268 state->base->count--;
1269 if (state->base->count == 0) {
1270 list_del(&state->base->stvlist);
1271 kfree(state->base);
1273 kfree(state);
1279 struct stv *state = fe->demodulator_priv;
1282 stop(state);
1285 state->symbol_rate = p->symbol_rate;
1286 stat = start(state, p);
1290 static int manage_matype_info(struct stv *state)
1292 if (!state->started)
1294 if (state->receive_mode == RCVMODE_DVBS2) {
1297 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
1299 state->feroll_off =
1301 state->is_vcm = (bbheader[0] & 0x10) == 0;
1302 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
1303 } else if (state->receive_mode == RCVMODE_DVBS) {
1304 state->is_vcm = 0;
1305 state->is_standard_broadcast = 1;
1306 state->feroll_off = FE_SAT_35;
1313 struct stv *state = fe->demodulator_priv;
1317 if (!get_signal_to_noise(state, &snrval)) {
1329 struct stv *state = fe->demodulator_priv;
1333 get_bit_error_rate(state, &n, &d);
1345 struct stv *state = fe->demodulator_priv;
1346 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1352 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
1357 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
1372 struct stv *state = fe->demodulator_priv;
1381 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
1384 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
1390 set_vth(state);
1406 if (state->receive_mode == RCVMODE_NONE) {
1407 state->receive_mode = cur_receive_mode;
1408 state->demod_lock_time = jiffies;
1409 state->first_time_lock = 1;
1411 get_signal_parameters(state);
1412 tracking_optimization(state);
1414 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1415 state->tscfgh);
1417 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1418 state->tscfgh | 0x01);
1419 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1420 state->tscfgh);
1423 if (state->receive_mode == RCVMODE_DVBS2) {
1426 read_reg(state,
1427 RSTV0910_P2_PDELSTATUS1 + state->regoff,
1433 read_reg(state,
1434 RSTV0910_P2_VSTATUSVIT + state->regoff,
1443 if (state->first_time_lock) {
1446 state->first_time_lock = 0;
1448 manage_matype_info(state);
1450 if (state->receive_mode == RCVMODE_DVBS2) {
1455 state->demod_bits &= ~0x84;
1456 write_reg(state,
1457 RSTV0910_P2_DEMOD + state->regoff,
1458 state->demod_bits);
1459 read_reg(state,
1460 RSTV0910_P2_PDELCTRL2 + state->regoff,
1464 write_reg(state,
1465 RSTV0910_P2_PDELCTRL2 + state->regoff,
1469 write_reg(state,
1470 RSTV0910_P2_PDELCTRL2 + state->regoff,
1473 state->berscale = 2;
1474 state->last_bernumerator = 0;
1475 state->last_berdenominator = 1;
1477 write_reg(state,
1478 RSTV0910_P2_ERRCTRL1 + state->regoff,
1479 BER_SRC_S2 | state->berscale);
1481 state->berscale = 2;
1482 state->last_bernumerator = 0;
1483 state->last_berdenominator = 1;
1485 write_reg(state,
1486 RSTV0910_P2_ERRCTRL1 + state->regoff,
1487 BER_SRC_S | state->berscale);
1490 write_reg(state,
1491 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
1496 write_reg(state,
1497 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
1499 set_vth_default(state);
1500 if (state->receive_mode == RCVMODE_DVBS)
1501 enable_puncture_rate(state,
1502 state->puncture_rate);
1506 if (state->is_vcm) {
1510 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
1514 if (mod_cod > state->mod_cod)
1515 state->mod_cod = mod_cod;
1544 struct stv *state = fe->demodulator_priv;
1548 if (state->receive_mode == RCVMODE_DVBS2) {
1570 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
1575 } else if (state->receive_mode == RCVMODE_DVBS) {
1576 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
1600 if (state->receive_mode != RCVMODE_NONE) {
1601 get_cur_symbol_rate(state, &symbolrate);
1611 struct stv *state = fe->demodulator_priv;
1618 state->tune_time = jiffies;
1639 struct stv *state = fe->demodulator_priv;
1640 u16 offs = state->nr ? 0x40 : 0;
1644 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1646 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
1653 static int wait_dis(struct stv *state, u8 flag, u8 val)
1657 u16 offs = state->nr ? 0x40 : 0;
1660 read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
1671 struct stv *state = fe->demodulator_priv;
1677 wait_dis(state, 0x40, 0x00);
1681 wait_dis(state, 0x20, 0x20);
1687 struct stv *state = fe->demodulator_priv;
1699 wait_dis(state, 0x40, 0x00);
1702 wait_dis(state, 0x20, 0x20);
1709 struct stv *state = fe->demodulator_priv;
1711 stop(state);
1753 static void stv0910_init_stats(struct stv *state)
1755 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1771 struct stv *state;
1774 state = kzalloc(sizeof(*state), GFP_KERNEL);
1775 if (!state)
1778 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
1779 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
1780 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
1782 state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);
1783 state->nr = nr;
1784 state->regoff = state->nr ? 0 : 0x200;
1785 state->search_range = 16000000;
1786 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
1787 state->receive_mode = RCVMODE_NONE;
1788 state->cur_scrambling_code = (~0U);
1789 state->single = cfg->single ? 1 : 0;
1794 state->base = base;
1806 state->base = base;
1807 if (probe(state) < 0) {
1815 state->fe.ops = stv0910_ops;
1816 state->fe.demodulator_priv = state;
1817 state->nr = nr;
1820 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
1822 stv0910_init_stats(state);
1824 return &state->fe;
1827 kfree(state);