media/dvb-frontends/stv0910.c

132 static int write_reg(struct stv *state, u16 reg, u8 val)
184 		status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
202 	return write_reg(state, field >> 16, new);
210 	write_reg(state, state->nr ? RSTV0910_P2_##_reg :	\
559 	write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
572 				write_reg(state, RSTV0910_P2_ACLC2S2Q +
575 				write_reg(state, RSTV0910_P2_ACLC2S2Q +
577 				write_reg(state, RSTV0910_P2_ACLC2S28 +
580 				write_reg(state, RSTV0910_P2_ACLC2S2Q +
582 				write_reg(state, RSTV0910_P2_ACLC2S216A +
585 				write_reg(state, RSTV0910_P2_ACLC2S2Q +
587 				write_reg(state, RSTV0910_P2_ACLC2S232A +
683 			status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
689 			status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
759 			write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
764 			write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
845 	write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
846 	write_reg(state, RSTV0910_NCOARSE2, odf);
847 	write_reg(state, RSTV0910_NCOARSE1, ndiv);
860 		write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
864 		write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
866 		write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
868 		write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
881 	write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
883 	write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
885 	write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
899 		write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
901 		write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
958 	return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
969 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
970 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
971 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
972 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
973 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
974 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1001 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
1002 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
1003 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
1004 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
1005 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
1006 	write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1024 		write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
1050 	write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1052 	write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1055 	write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1059 	write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1066 	write_reg(state, RSTV0910_P2_FECM  + state->regoff, 0x00);
1067 	write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1072 	write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1073 	write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1074 	write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1075 	write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1076 	write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1077 	write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1079 	write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1080 	write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1081 	write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1082 	write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1088 	write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1089 	write_reg(state, RSTV0910_TSTRES0, 0);
1093 	write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1095 	write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1103 	write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1105 	write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
1108 	write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1110 	write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1113 	write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1114 	write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1116 	write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1118 	write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1132 	write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1133 	write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1134 	write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1135 	write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1153 	write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1155 	write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1157 	write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1159 	write_reg(state, RSTV0910_OUTCFG,    0x00); /* OUTCFG */
1160 	write_reg(state, RSTV0910_PADCFG,    0x05); /* RFAGC Pads Dev = 05 */
1161 	write_reg(state, RSTV0910_SYNTCTRL,  0x02); /* SYNTCTRL */
1162 	write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1163 	write_reg(state, RSTV0910_CFGEXT,    0x02); /* CFGEXT */
1166 		write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
1168 		write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
1170 	write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1171 	write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
1173 	write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1174 	write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1175 	write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1176 	write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1178 	write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1179 	write_reg(state, RSTV0910_TSTRES0, 0x00);
1181 	write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1182 	write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1184 	write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1185 	write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1190 	write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1191 	write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1192 	write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
1193 	write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1195 	write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1197 	write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1198 	write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1199 	write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
1200 	write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1202 	write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1205 	write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1206 	write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1207 	write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1208 	write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1210 	write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1211 	write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1213 	write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
1214 	write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
1216 	write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
1217 	write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
1245 	if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
1251 			"%s() write_reg failure (enable=%d)\n",
1414 		write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1417 		write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1419 		write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1456 				write_reg(state,
1464 				write_reg(state,
1469 				write_reg(state,
1477 				write_reg(state,
1485 				write_reg(state,
1490 			write_reg(state,
1496 			write_reg(state,
1644 		return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1646 		return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);