media/dvb-frontends/stb0899_algo.c

166 	u8 reg;
172 	reg = stb0899_read_reg(state, STB0899_TLIR);
173 	lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
241 	u8 reg;
245 	reg = stb0899_read_reg(state, STB0899_CFD);
246 	STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
247 	stb0899_write_reg(state, STB0899_CFD, reg);
249 	reg = stb0899_read_reg(state, STB0899_DSTATUS);
250 	dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
251 	if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
273 	u8 reg;
279 	reg = stb0899_read_reg(state, STB0899_CFD);
280 	STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
281 	stb0899_write_reg(state, STB0899_CFD, reg);
294 				reg = stb0899_read_reg(state, STB0899_CFD);
295 				STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
296 				stb0899_write_reg(state, STB0899_CFD, reg);
328 	u8 reg;
333 	reg = stb0899_read_reg(state, STB0899_TSTRES);
334 	STB0899_SETFIELD_VAL(FRESACS, reg, 1);
335 	stb0899_write_reg(state, STB0899_TSTRES, reg);
337 	reg = stb0899_read_reg(state, STB0899_TSTRES);
338 	STB0899_SETFIELD_VAL(FRESACS, reg, 0);
339 	stb0899_write_reg(state, STB0899_TSTRES, reg);
356 		reg = stb0899_read_reg(state, STB0899_VSTATUS);
357 		lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
358 		loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
381 	u8 reg;
400 				reg = stb0899_read_reg(state, STB0899_CFD);
401 				STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
402 				stb0899_write_reg(state, STB0899_CFD, reg);
419 		reg = stb0899_read_reg(state, STB0899_IQSWAP);
420 		if (STB0899_GETFIELD(SYM, reg))
495 	u8 bclc, reg;
562 	reg = stb0899_read_reg(state, STB0899_TSTRES);
563 	STB0899_SETFIELD_VAL(FRESRS, reg, 1);
564 	stb0899_write_reg(state, STB0899_TSTRES, reg);
570 	reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
571 	STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
572 	stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
584 		reg = stb0899_read_reg(state, STB0899_CFD);
585 		STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
586 		stb0899_write_reg(state, STB0899_CFD, reg);
639 						reg = stb0899_read_reg(state, STB0899_PLPARM);
640 						internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
670 		reg = stb0899_read_reg(state, STB0899_BCLC);
674 			STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
675 			stb0899_write_reg(state, STB0899_BCLC, reg);
679 			STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
680 			stb0899_write_reg(state, STB0899_BCLC, reg);
684 			STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
685 			stb0899_write_reg(state, STB0899_BCLC, reg);
689 			STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
690 			stb0899_write_reg(state, STB0899_BCLC, reg);
699 			STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
700 			stb0899_write_reg(state, STB0899_BCLC, reg);
707 		reg = stb0899_read_reg(state, STB0899_TSTRES);
708 		STB0899_SETFIELD_VAL(FRESRS, reg, 0);
709 		stb0899_write_reg(state, STB0899_TSTRES, reg);
712 		reg = stb0899_read_reg(state, STB0899_CFD);
713 		STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
714 		stb0899_write_reg(state, STB0899_CFD, reg);
730 	u32 uwp1, uwp2, uwp3, reg;
751 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
752 	STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
753 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
762 	u32 reg;
764 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
765 	STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
766 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
842 	u32 correction, freq_adj, band_lim, decim_cntrl, reg;
878 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
879 	STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
880 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
900 	u32 reg;
935 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
936 		STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
937 		STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
938 		STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
939 		STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
940 		STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
941 		stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
954 	u32 reg;
958 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
959 	STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
960 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
971 	u32 range, reg;
1002 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1003 	STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1004 	STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1005 	STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1006 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1015 	u32 reg;
1018 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1019 	STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1020 	STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1021 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1038 	u32 reg = 0;
1041 	STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1042 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1055 	reg = 0;
1056 	STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1057 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1069 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1070 	STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1071 	STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1072 	STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1073 	STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1074 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1087 	u32 reg;
1090 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1091 		dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1092 		if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1094 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1095 		dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1096 		uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1097 		csm = STB0899_GETFIELD(CSM_LOCK, reg);
1121 	u8 reg;
1124 		reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1125 		dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1126 		lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1273 	u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1281 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1282 	decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1309 	u32 reg, csm1;
1335 	reg = stb0899_read_reg(state, STB0899_TSTRES);
1336 	STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1337 	stb0899_write_reg(state, STB0899_TSTRES, reg);
1352 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1353 	STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  4);
1354 	STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1355 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1357 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1358 	STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1359 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1364 	reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1367 		STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1370 		STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1373 	stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1391 			reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1392 			STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1393 			stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1401 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1402 		iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1404 		STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1405 		stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1421 				reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1422 				STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1423 				stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1437 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1438 		modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1439 		pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1468 			reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1469 			STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1470 			stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1474 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1475 		STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1476 		stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1487 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1488 		if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1496 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1497 		internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1498 		internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1499 		internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1502 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1503 		STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  3);
1507 			STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1509 		stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1511 		reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1512 		STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1513 		stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1517 	reg = stb0899_read_reg(state, STB0899_TSTRES);
1518 	STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1519 	stb0899_write_reg(state, STB0899_TSTRES, reg);