media/dvb-frontends/si2165.c

62 	int ret;
67 	ret = regmap_bulk_write(state->regmap, reg, src, count);
69 	if (ret)
70 		dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret);
72 	return ret;
78 	int ret = regmap_bulk_read(state->regmap, reg, val, count);
80 	if (ret) {
81 		dev_err(&state->client->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n",
82 			__func__, state->config.i2c_addr, reg, ret);
83 		return ret;
96 	int ret = regmap_read(state->regmap, reg, &val_tmp);
99 	return ret;
107 	int ret = si2165_read(state, reg, buf, 2);
110 	return ret;
118 	int ret = si2165_read(state, reg, buf, 3);
121 	return ret;
159 		int ret = si2165_readreg8(state, reg, &tmp);
161 		if (ret < 0)
162 			return ret;
184 	int ret;
187 		ret = si2165_writereg8(state, regs[i].reg, regs[i].val);
188 		if (ret < 0)
189 			return ret;
269 	int ret;
274 		ret = si2165_readreg8(state, REG_INIT_DONE, &val);
275 		if (ret < 0)
276 			return ret;
289 	int ret;
325 		ret = si2165_write(state, REG_DCOM_CONTROL_BYTE, buf_ctrl, 4);
326 		if (ret < 0)
328 		ret = si2165_write(state, REG_DCOM_ADDR, data + offset + 4, 4);
329 		if (ret < 0)
335 			ret = si2165_write(state, REG_DCOM_DATA,
337 			if (ret < 0)
358 	return ret;
363 	/* int ret; */
366 	int ret;
388 	ret = request_firmware(&fw, fw_file, &state->client->dev);
389 	if (ret) {
403 		ret = -EINVAL;
410 		ret = -EINVAL;
416 		ret = -EINVAL;
426 	ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
427 	if (ret < 0)
430 	ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
431 	if (ret < 0)
434 	ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
435 	if (ret < 0)
439 	ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
440 	if (ret < 0)
442 	ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
443 	if (ret < 0)
445 	ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02);
446 	if (ret < 0)
455 	ret = si2165_upload_firmware_block(state, data, len, &offset, 1);
456 	if (ret < 0)
459 	ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version);
460 	if (ret < 0)
464 	ret = si2165_writereg8(state, REG_RST_CRC, 0x01);
465 	if (ret)
468 	ret = si2165_upload_firmware_block(state, data, len,
470 	if (ret < 0) {
477 	ret = si2165_readreg16(state, REG_CRC, &val16);
478 	if (ret)
485 		ret = -EINVAL;
489 	ret = si2165_upload_firmware_block(state, data, len, &offset, 5);
490 	if (ret)
497 		ret = -EINVAL;
502 	ret = si2165_writereg_mask8(state, REG_WDOG_AND_BOOT, 0x02, 0x02);
503 	if (ret < 0)
507 	ret = si2165_writereg_mask8(state, REG_EN_RST_ERROR, 0x01, 0x01);
508 	if (ret < 0)
513 	ret = 0;
519 	return ret;
524 	int ret = 0;
533 	ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
534 	if (ret < 0)
537 	ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01);
538 	if (ret < 0)
541 	ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
542 	if (ret < 0)
550 	ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00);
551 	if (ret < 0)
553 	ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01);
554 	if (ret < 0)
556 	ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00);
557 	if (ret < 0)
559 	ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07);
560 	if (ret < 0)
563 	ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00);
564 	if (ret < 0)
566 	ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00);
567 	if (ret < 0)
570 	ret = si2165_init_pll(state);
571 	if (ret < 0)
575 	ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01);
576 	if (ret < 0)
579 	ret = si2165_writereg8(state, REG_START_INIT, 0x01);
580 	if (ret < 0)
582 	ret = si2165_wait_init_done(state);
583 	if (ret < 0)
587 	ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00);
588 	if (ret < 0)
592 	ret = si2165_writereg16(state, REG_BER_PKT,
594 	if (ret < 0)
597 	ret = si2165_readreg8(state, REG_PATCH_VERSION, &patch_version);
598 	if (ret < 0)
601 	ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00);
602 	if (ret < 0)
606 	ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
607 	if (ret < 0)
610 	ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val);
611 	if (ret < 0)
615 		ret = si2165_upload_firmware(state);
616 		if (ret < 0)
621 	ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20);
622 	if (ret < 0)
623 		return ret;
624 	ret = si2165_writereg16(state, REG_TS_TRI, 0x00fe);
625 	if (ret < 0)
626 		return ret;
627 	ret = si2165_writereg24(state, REG_TS_SLR, 0x555555);
628 	if (ret < 0)
629 		return ret;
630 	ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01);
631 	if (ret < 0)
632 		return ret;
633 	ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00);
634 	if (ret < 0)
635 		return ret;
647 	return ret;
652 	int ret;
656 	ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00);
657 	if (ret < 0)
658 		return ret;
660 	ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
661 	if (ret < 0)
662 		return ret;
668 	int ret;
680 		ret = si2165_readreg8(state, REG_CHECK_SIGNAL, &u8tmp);
681 		if (ret < 0)
682 			return ret;
694 		ret = si2165_readreg8(state, REG_PS_LOCK, &u8tmp);
695 		if (ret < 0)
696 			return ret;
707 	ret = si2165_readreg8(state, REG_FEC_LOCK, &u8tmp);
708 	if (ret < 0)
709 		return ret;
720 		ret = si2165_readreg24(state, REG_C_N, &u32tmp);
721 		if (ret < 0)
722 			return ret;
744 			ret = si2165_writereg8(state, REG_BER_RST, 0x01);
745 			if (ret < 0)
746 				return ret;
761 			ret = si2165_readreg8(state, REG_BER_AVAIL, &u8tmp);
762 			if (ret < 0)
763 				return ret;
768 				ret = si2165_readreg24(state, REG_BER_BIT,
770 				if (ret < 0)
771 					return ret;
779 				ret = si2165_writereg8(state,
781 				if (ret < 0)
782 					return ret;
898 	int ret;
917 	ret = si2165_adjust_pll_divl(state, 12);
918 	if (ret < 0)
919 		return ret;
922 	ret = si2165_writereg16(state, REG_T_BANDWIDTH, bw10k);
923 	if (ret < 0)
924 		return ret;
925 	ret = si2165_set_oversamp(state, dvb_rate);
926 	if (ret < 0)
927 		return ret;
929 	ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs));
930 	if (ret < 0)
931 		return ret;
967 	int ret;
978 	ret = si2165_adjust_pll_divl(state, 14);
979 	if (ret < 0)
980 		return ret;
983 	ret = si2165_set_oversamp(state, dvb_rate);
984 	if (ret < 0)
985 		return ret;
1008 	ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp);
1009 	if (ret < 0)
1010 		return ret;
1012 	ret = si2165_writereg32(state, REG_LOCK_TIMEOUT, 0x007a1200);
1013 	if (ret < 0)
1014 		return ret;
1016 	ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs));
1017 	if (ret < 0)
1018 		return ret;
1036 	int ret;
1040 	ret = si2165_set_if_freq_shift(state);
1041 	if (ret < 0)
1042 		return ret;
1046 		ret = si2165_set_frontend_dvbt(fe);
1047 		if (ret < 0)
1048 			return ret;
1051 		ret = si2165_set_frontend_dvbc(fe);
1052 		if (ret < 0)
1053 			return ret;
1060 	ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
1061 	if (ret < 0)
1062 		return ret;
1068 	ret = si2165_set_if_freq_shift(state);
1069 	if (ret < 0)
1070 		return ret;
1073 	ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
1074 	if (ret < 0)
1075 		return ret;
1076 	ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
1077 	if (ret < 0)
1078 		return ret;
1081 	ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
1082 	if (ret < 0)
1083 		return ret;
1085 	ret = si2165_writereg32(state, REG_GP_REG0_LSB, 0x00000000);
1086 	if (ret < 0)
1087 		return ret;
1090 	ret = si2165_write_reg_list(state, adc_rewrite,
1092 	if (ret < 0)
1093 		return ret;
1096 	ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01);
1097 	if (ret < 0)
1098 		return ret;
1100 	ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
1101 	if (ret < 0)
1102 		return ret;
1150 	int ret = 0;
1163 		ret = -ENOMEM;
1170 		ret = PTR_ERR(state->regmap);
1185 		ret = -EINVAL;
1197 	ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
1198 	if (ret < 0)
1201 	ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
1202 	if (ret < 0)
1207 	ret = si2165_readreg8(state, REG_CHIP_REVCODE, &state->chip_revcode);
1208 	if (ret < 0)
1211 	ret = si2165_readreg8(state, REV_CHIP_TYPE, &state->chip_type);
1212 	if (ret < 0)
1216 	ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
1217 	if (ret < 0)
1267 	ret = -ENODEV;
1270 	dev_dbg(&client->dev, "failed=%d\n", ret);
1271 	return ret;