media/dvb-frontends/lgs8gl5.c

60 lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
65 		.addr  = state->config->demod_address,
71 	ret = i2c_transfer(state->i2c, &msg, 1);
81 lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg)
88 			.addr  = state->config->demod_address,
94 			.addr  = state->config->demod_address,
101 	ret = i2c_transfer(state->i2c, msg, 2);
110 lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
112 	lgs8gl5_read_reg(state, reg);
113 	lgs8gl5_write_reg(state, reg, data);
121 lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
129 			.addr  = state->config->demod_address + 2,
135 			.addr  = state->config->demod_address + 2,
141 			.addr  = state->config->demod_address + 2,
148 	ret = i2c_transfer(state->i2c, msg, 3);
154 lgs8gl5_soft_reset(struct lgs8gl5_state *state)
160 	val = lgs8gl5_read_reg(state, REG_RESET);
161 	lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF);
162 	lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF);
169 lgs8gl5_start_demod(struct lgs8gl5_state *state)
176 	lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
177 	lgs8gl5_soft_reset(state);
178 	lgs8gl5_update_reg(state, REG_07, 0x10);
179 	lgs8gl5_update_reg(state, REG_07, 0x10);
180 	lgs8gl5_write_reg(state, REG_09, 0x0e);
181 	lgs8gl5_write_reg(state, REG_0A, 0xe5);
182 	lgs8gl5_write_reg(state, REG_0B, 0x35);
183 	lgs8gl5_write_reg(state, REG_0C, 0x30);
185 	lgs8gl5_update_reg(state, REG_03, 0x00);
186 	lgs8gl5_update_reg(state, REG_7E, 0x01);
187 	lgs8gl5_update_alt_reg(state, 0xc5, 0x00);
188 	lgs8gl5_update_reg(state, REG_04, 0x02);
189 	lgs8gl5_update_reg(state, REG_37, 0x01);
190 	lgs8gl5_soft_reset(state);
194 		val = lgs8gl5_read_reg(state, REG_STRENGTH);
205 		val = lgs8gl5_read_reg(state, REG_STATUS);
214 	lgs8gl5_write_reg(state, REG_7D, lgs8gl5_read_reg(state, REG_A2));
215 	lgs8gl5_soft_reset(state);
222 	struct lgs8gl5_state *state = fe->demodulator_priv;
226 	lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
227 	lgs8gl5_soft_reset(state);
228 	lgs8gl5_update_reg(state, REG_07, 0x10);
229 	lgs8gl5_update_reg(state, REG_07, 0x10);
230 	lgs8gl5_write_reg(state, REG_09, 0x0e);
231 	lgs8gl5_write_reg(state, REG_0A, 0xe5);
232 	lgs8gl5_write_reg(state, REG_0B, 0x35);
233 	lgs8gl5_write_reg(state, REG_0C, 0x30);
242 	struct lgs8gl5_state *state = fe->demodulator_priv;
243 	u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
244 	u8 flags = lgs8gl5_read_reg(state, REG_STATUS);
273 	struct lgs8gl5_state *state = fe->demodulator_priv;
274 	u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
284 	struct lgs8gl5_state *state = fe->demodulator_priv;
285 	u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
305 	struct lgs8gl5_state *state = fe->demodulator_priv;
318 	/* lgs8gl5_set_inversion(state, p->inversion); */
320 	lgs8gl5_start_demod(state);
330 	struct lgs8gl5_state *state = fe->demodulator_priv;
332 	u8 inv = lgs8gl5_read_reg(state, REG_INVERSION);
362 	struct lgs8gl5_state *state = fe->demodulator_priv;
363 	kfree(state);
373 	struct lgs8gl5_state *state = NULL;
377 	/* Allocate memory for the internal state */
378 	state = kzalloc(sizeof(struct lgs8gl5_state), GFP_KERNEL);
379 	if (state == NULL)
382 	/* Setup the state */
383 	state->config = config;
384 	state->i2c    = i2c;
387 	if (lgs8gl5_read_reg(state, REG_RESET) < 0)
391 	memcpy(&state->frontend.ops, &lgs8gl5_ops,
393 	state->frontend.demodulator_priv = state;
394 	return &state->frontend;
397 	kfree(state);