media/dvb-frontends/lgdt3306a.c

123 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
126 	u8 buf[] = { reg >> 8, reg & 0xff, val };
132 	dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
147 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
155 		  .flags = I2C_M_RD, .buf = val, .len = 1 },
168 	dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
185 	u8 val;
190 	ret = lgdt3306a_read_reg(state, reg, &val);
194 	val &= ~(1 << bit);
195 	val |= (onoff & 1) << bit;
197 	ret = lgdt3306a_write_reg(state, reg, val);
226 	u8 val;
244 	ret = lgdt3306a_read_reg(state, 0x0070, &val);
248 	val |= 0x10; /* TPCLKSUPB=0x10 */
251 		val &= ~0x10;
253 	ret = lgdt3306a_write_reg(state, 0x0070, val);
264 	u8 val;
269 	ret = lgdt3306a_read_reg(state, 0x0070, &val);
273 	val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
276 		val |= 0x04;
278 		val |= 0x02;
280 	ret = lgdt3306a_write_reg(state, 0x0070, val);
290 	u8 val;
296 		ret = lgdt3306a_read_reg(state, 0x0070, &val);
303 		val &= ~0xa8;
304 		ret = lgdt3306a_write_reg(state, 0x0070, val);
319 		ret = lgdt3306a_read_reg(state, 0x0070, &val);
323 		val |= 0xa8; /* enable bus */
324 		ret = lgdt3306a_write_reg(state, 0x0070, val);
383 	u8 val;
389 	ret = lgdt3306a_read_reg(state, 0x0002, &val);
390 	val &= 0xf7; /* SPECINVAUTO Off */
391 	val |= 0x04; /* SPECINV On */
392 	ret = lgdt3306a_write_reg(state, 0x0002, val);
402 	ret = lgdt3306a_read_reg(state, 0x0009, &val);
403 	val &= 0xe3;
404 	val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
405 	ret = lgdt3306a_write_reg(state, 0x0009, val);
410 	ret = lgdt3306a_read_reg(state, 0x0009, &val);
411 	val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
412 	ret = lgdt3306a_write_reg(state, 0x0009, val);
417 	ret = lgdt3306a_read_reg(state, 0x000d, &val);
418 	val &= 0xbf; /* SAMPLING4XFEN=0 */
419 	ret = lgdt3306a_write_reg(state, 0x000d, val);
479 	ret = lgdt3306a_read_reg(state, 0x001e, &val);
480 	val &= 0x0f;
481 	val |= 0xa0;
482 	ret = lgdt3306a_write_reg(state, 0x001e, val);
488 	ret = lgdt3306a_read_reg(state, 0x211f, &val);
489 	val &= 0xef;
490 	ret = lgdt3306a_write_reg(state, 0x211f, val);
494 	ret = lgdt3306a_read_reg(state, 0x1061, &val);
495 	val &= 0xf8;
496 	val |= 0x04;
497 	ret = lgdt3306a_write_reg(state, 0x1061, val);
499 	ret = lgdt3306a_read_reg(state, 0x103d, &val);
500 	val &= 0xcf;
501 	ret = lgdt3306a_write_reg(state, 0x103d, val);
505 	ret = lgdt3306a_read_reg(state, 0x2141, &val);
506 	val &= 0x3f;
507 	ret = lgdt3306a_write_reg(state, 0x2141, val);
509 	ret = lgdt3306a_read_reg(state, 0x2135, &val);
510 	val &= 0x0f;
511 	val |= 0x70;
512 	ret = lgdt3306a_write_reg(state, 0x2135, val);
514 	ret = lgdt3306a_read_reg(state, 0x0003, &val);
515 	val &= 0xf7;
516 	ret = lgdt3306a_write_reg(state, 0x0003, val);
518 	ret = lgdt3306a_read_reg(state, 0x001c, &val);
519 	val &= 0x7f;
520 	ret = lgdt3306a_write_reg(state, 0x001c, val);
523 	ret = lgdt3306a_read_reg(state, 0x2179, &val);
524 	val &= 0xf8;
525 	ret = lgdt3306a_write_reg(state, 0x2179, val);
527 	ret = lgdt3306a_read_reg(state, 0x217a, &val);
528 	val &= 0xf8;
529 	ret = lgdt3306a_write_reg(state, 0x217a, val);
543 	u8 val;
554 	ret = lgdt3306a_read_reg(state, 0x0002, &val);
555 	val &= 0xfb; /* SPECINV Off */
556 	val |= 0x08; /* SPECINVAUTO On */
557 	ret = lgdt3306a_write_reg(state, 0x0002, val);
562 	ret = lgdt3306a_read_reg(state, 0x0009, &val);
563 	val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
564 	ret = lgdt3306a_write_reg(state, 0x0009, val);
569 	ret = lgdt3306a_read_reg(state, 0x0009, &val);
570 	val &= 0xfc;
573 		val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */
575 		val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */
577 	ret = lgdt3306a_write_reg(state, 0x0009, val);
582 	ret = lgdt3306a_read_reg(state, 0x101a, &val);
583 	val &= 0xf8;
585 		val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
587 		val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
589 	ret = lgdt3306a_write_reg(state, 0x101a, val);
594 	ret = lgdt3306a_read_reg(state, 0x000d, &val);
595 	val &= 0xbf;
596 	val |= 0x40; /* SAMPLING4XFEN=1 */
597 	ret = lgdt3306a_write_reg(state, 0x000d, val);
602 	ret = lgdt3306a_read_reg(state, 0x0024, &val);
603 	val &= 0x00;
604 	ret = lgdt3306a_write_reg(state, 0x0024, val);
609 	ret = lgdt3306a_read_reg(state, 0x000a, &val);
610 	val &= 0xfd;
611 	val |= 0x02;
612 	ret = lgdt3306a_write_reg(state, 0x000a, val);
617 	ret = lgdt3306a_read_reg(state, 0x2849, &val);
618 	val &= 0xdf;
619 	ret = lgdt3306a_write_reg(state, 0x2849, val);
624 	ret = lgdt3306a_read_reg(state, 0x302b, &val);
625 	val &= 0x7f;  /* SELFSYNCFINDEN_CQS=0; disable auto reset */
626 	ret = lgdt3306a_write_reg(state, 0x302b, val);
817 	u8 val;
867 		ret = lgdt3306a_read_reg(state, 0x0005, &val);
870 		val &= 0xc0;
871 		val |= 0x25;
872 		ret = lgdt3306a_write_reg(state, 0x0005, val);
880 		ret = lgdt3306a_read_reg(state, 0x000d, &val);
883 		val &= 0xc0;
884 		val |= 0x18;
885 		ret = lgdt3306a_write_reg(state, 0x000d, val);
891 		ret = lgdt3306a_read_reg(state, 0x0005, &val);
894 		val &= 0xc0;
895 		val |= 0x25;
896 		ret = lgdt3306a_write_reg(state, 0x0005, val);
904 		ret = lgdt3306a_read_reg(state, 0x000d, &val);
907 		val &= 0xc0;
908 		val |= 0x19;
909 		ret = lgdt3306a_write_reg(state, 0x000d, val);
928 	ret = lgdt3306a_read_reg(state, 0x103c, &val);
929 	val &= 0x0f;
930 	val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
931 	ret = lgdt3306a_write_reg(state, 0x103c, val);
934 	ret = lgdt3306a_read_reg(state, 0x103d, &val);
935 	val &= 0xfc;
936 	val |= 0x03;
937 	ret = lgdt3306a_write_reg(state, 0x103d, val);
940 	ret = lgdt3306a_read_reg(state, 0x1036, &val);
941 	val &= 0xf0;
942 	val |= 0x0c;
943 	ret = lgdt3306a_write_reg(state, 0x1036, val);
946 	ret = lgdt3306a_read_reg(state, 0x211f, &val);
947 	val &= 0xef; /* do not use imaginary of CIR */
948 	ret = lgdt3306a_write_reg(state, 0x211f, val);
951 	ret = lgdt3306a_read_reg(state, 0x2849, &val);
952 	val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
953 	ret = lgdt3306a_write_reg(state, 0x2849, val);
1071 	u8 val;
1076 	ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1079 	snrRef = val & 0x3f;
1085 	ret = lgdt3306a_read_reg(state, 0x2191, &val);
1088 	nCombDet = (val & 0x80) >> 7;
1090 	ret = lgdt3306a_read_reg(state, 0x2180, &val);
1093 	fbDlyCir = (val & 0x03) << 8;
1095 	ret = lgdt3306a_read_reg(state, 0x2181, &val);
1098 	fbDlyCir |= val;
1104 	ret = lgdt3306a_read_reg(state, 0x1061, &val);
1107 	val &= 0xf8;
1112 		val |= 0x00; /* final bandwidth = 0 */
1114 		val |= 0x04; /* final bandwidth = 4 */
1116 	ret = lgdt3306a_write_reg(state, 0x1061, val);
1121 	ret = lgdt3306a_read_reg(state, 0x0024, &val);
1124 	val &= 0x0f;
1126 		val |= 0x50;
1128 	ret = lgdt3306a_write_reg(state, 0x0024, val);
1133 	ret = lgdt3306a_read_reg(state, 0x103d, &val);
1136 	val &= 0xcf;
1137 	val |= 0x20;
1138 	ret = lgdt3306a_write_reg(state, 0x103d, val);
1146 	u8 val = 0;
1149 	ret = lgdt3306a_read_reg(state, 0x0081, &val);
1153 	if (val & 0x80)	{
1157 	if (val & 0x08) {
1158 		ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1161 		val = val >> 2;
1162 		if (val & 0x01) {
1178 	u8 val = 0;
1188 		ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1192 		if ((val & 0x80) == 0x80)
1202 		ret = lgdt3306a_read_reg(state, 0x0080, &val);
1206 		if ((val & 0x40) == 0x40)
1218 			ret = lgdt3306a_read_reg(state, 0x1094, &val);
1222 			if ((val & 0x80) == 0x80)
1236 			ret = lgdt3306a_read_reg(state, 0x0080, &val);
1240 			if ((val & 0x10) == 0x10)
1263 	u8 val = 0;
1267 	ret = lgdt3306a_read_reg(state, 0x0080, &val);
1270 	lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
1279 	u8 val = 0;
1289 	ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1292 	snrRef = val & 0x3f;
1295 	ret = lgdt3306a_read_reg(state, 0x2199, &val);
1298 	mainStrong = (val & 0x40) >> 6;
1300 	ret = lgdt3306a_read_reg(state, 0x0090, &val);
1303 	aiccrejStatus = (val & 0xf0) >> 4;
1313 		ret = lgdt3306a_read_reg(state, 0x2135, &val);
1316 		val &= 0x0f;
1317 		val |= 0xa0;
1318 		ret = lgdt3306a_write_reg(state, 0x2135, val);
1322 		ret = lgdt3306a_read_reg(state, 0x2141, &val);
1325 		val &= 0x3f;
1326 		val |= 0x80;
1327 		ret = lgdt3306a_write_reg(state, 0x2141, val);
1335 		ret = lgdt3306a_read_reg(state, 0x2135, &val);
1338 		val &= 0x0f;
1339 		val |= 0x70;
1340 		ret = lgdt3306a_write_reg(state, 0x2135, val);
1344 		ret = lgdt3306a_read_reg(state, 0x2141, &val);
1347 		val &= 0x3f;
1348 		val |= 0x40;
1349 		ret = lgdt3306a_write_reg(state, 0x2141, val);
1424 	u8 val;
1427 	ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1431 	return val;
1641 	u8 val;
1657 		ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1661 		if(val & 0x04)
1799 	u8 val;
1819 	ret = lgdt3306a_read_reg(state, 0x0000, &val);
1822 	if ((val & 0x74) != 0x74) {
1823 		pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
1829 	ret = lgdt3306a_read_reg(state, 0x0001, &val);
1832 	if ((val & 0xf6) != 0xc6) {
1833 		pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
1839 	ret = lgdt3306a_read_reg(state, 0x0002, &val);
1842 	if ((val & 0x73) != 0x03) {
1843 		pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));