Lines Matching refs:state
118 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
119 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
123 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
128 .addr = state->cfg->i2c_addr, .flags = 0,
134 ret = i2c_transfer(state->i2c_adap, &msg, 1);
147 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
152 { .addr = state->cfg->i2c_addr,
154 { .addr = state->cfg->i2c_addr,
158 ret = i2c_transfer(state->i2c_adap, msg, 2);
162 state->cfg->i2c_addr, reg, ret);
173 #define read_reg(state, reg) \
176 int ret = lgdt3306a_read_reg(state, reg, &__val); \
182 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
190 ret = lgdt3306a_read_reg(state, reg, &val);
197 ret = lgdt3306a_write_reg(state, reg, val);
205 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
211 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
216 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
223 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
231 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
240 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
244 ret = lgdt3306a_read_reg(state, 0x0070, &val);
253 ret = lgdt3306a_write_reg(state, 0x0070, val);
260 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
269 ret = lgdt3306a_read_reg(state, 0x0070, &val);
280 ret = lgdt3306a_write_reg(state, 0x0070, val);
287 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
296 ret = lgdt3306a_read_reg(state, 0x0070, &val);
304 ret = lgdt3306a_write_reg(state, 0x0070, val);
309 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
315 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
319 ret = lgdt3306a_read_reg(state, 0x0070, &val);
324 ret = lgdt3306a_write_reg(state, 0x0070, val);
335 struct lgdt3306a_state *state = fe->demodulator_priv;
339 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
343 static int lgdt3306a_power(struct lgdt3306a_state *state,
352 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
357 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
363 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
368 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
374 lgdt3306a_DumpAllRegs(state);
381 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
389 ret = lgdt3306a_read_reg(state, 0x0002, &val);
392 ret = lgdt3306a_write_reg(state, 0x0002, val);
397 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
402 ret = lgdt3306a_read_reg(state, 0x0009, &val);
405 ret = lgdt3306a_write_reg(state, 0x0009, val);
410 ret = lgdt3306a_read_reg(state, 0x0009, &val);
412 ret = lgdt3306a_write_reg(state, 0x0009, val);
417 ret = lgdt3306a_read_reg(state, 0x000d, &val);
419 ret = lgdt3306a_write_reg(state, 0x000d, val);
426 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
431 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
432 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
433 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
436 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
437 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
438 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
441 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
442 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
443 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
446 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
447 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
448 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
454 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
459 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
460 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
461 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
464 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
465 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
466 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
469 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
470 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
471 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
474 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
475 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
476 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
479 ret = lgdt3306a_read_reg(state, 0x001e, &val);
482 ret = lgdt3306a_write_reg(state, 0x001e, val);
484 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
486 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
488 ret = lgdt3306a_read_reg(state, 0x211f, &val);
490 ret = lgdt3306a_write_reg(state, 0x211f, val);
492 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
494 ret = lgdt3306a_read_reg(state, 0x1061, &val);
497 ret = lgdt3306a_write_reg(state, 0x1061, val);
499 ret = lgdt3306a_read_reg(state, 0x103d, &val);
501 ret = lgdt3306a_write_reg(state, 0x103d, val);
503 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
505 ret = lgdt3306a_read_reg(state, 0x2141, &val);
507 ret = lgdt3306a_write_reg(state, 0x2141, val);
509 ret = lgdt3306a_read_reg(state, 0x2135, &val);
512 ret = lgdt3306a_write_reg(state, 0x2135, val);
514 ret = lgdt3306a_read_reg(state, 0x0003, &val);
516 ret = lgdt3306a_write_reg(state, 0x0003, val);
518 ret = lgdt3306a_read_reg(state, 0x001c, &val);
520 ret = lgdt3306a_write_reg(state, 0x001c, val);
523 ret = lgdt3306a_read_reg(state, 0x2179, &val);
525 ret = lgdt3306a_write_reg(state, 0x2179, val);
527 ret = lgdt3306a_read_reg(state, 0x217a, &val);
529 ret = lgdt3306a_write_reg(state, 0x217a, val);
532 ret = lgdt3306a_soft_reset(state);
541 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
549 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
554 ret = lgdt3306a_read_reg(state, 0x0002, &val);
557 ret = lgdt3306a_write_reg(state, 0x0002, val);
562 ret = lgdt3306a_read_reg(state, 0x0009, &val);
564 ret = lgdt3306a_write_reg(state, 0x0009, val);
569 ret = lgdt3306a_read_reg(state, 0x0009, &val);
577 ret = lgdt3306a_write_reg(state, 0x0009, val);
582 ret = lgdt3306a_read_reg(state, 0x101a, &val);
589 ret = lgdt3306a_write_reg(state, 0x101a, val);
594 ret = lgdt3306a_read_reg(state, 0x000d, &val);
597 ret = lgdt3306a_write_reg(state, 0x000d, val);
602 ret = lgdt3306a_read_reg(state, 0x0024, &val);
604 ret = lgdt3306a_write_reg(state, 0x0024, val);
609 ret = lgdt3306a_read_reg(state, 0x000a, &val);
612 ret = lgdt3306a_write_reg(state, 0x000a, val);
617 ret = lgdt3306a_read_reg(state, 0x2849, &val);
619 ret = lgdt3306a_write_reg(state, 0x2849, val);
624 ret = lgdt3306a_read_reg(state, 0x302b, &val);
626 ret = lgdt3306a_write_reg(state, 0x302b, val);
631 ret = lgdt3306a_soft_reset(state);
640 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
649 ret = lgdt3306a_set_vsb(state);
654 ret = lgdt3306a_set_qam(state, p->modulation);
662 state->current_modulation = p->modulation;
670 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
691 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
698 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
702 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
710 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
714 static int lgdt3306a_set_if(struct lgdt3306a_state *state,
723 if_freq_khz = state->cfg->vsb_if_khz;
728 if_freq_khz = state->cfg->qam_if_khz;
760 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
763 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
776 struct lgdt3306a_state *state = fe->demodulator_priv;
778 if (state->cfg->deny_i2c_rptr) {
779 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
785 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
788 static int lgdt3306a_sleep(struct lgdt3306a_state *state)
793 state->current_frequency = -1; /* force re-tune, when we wake */
795 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
799 ret = lgdt3306a_power(state, 0); /* power down */
808 struct lgdt3306a_state *state = fe->demodulator_priv;
810 return lgdt3306a_sleep(state);
815 struct lgdt3306a_state *state = fe->demodulator_priv;
823 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
828 ret = lgdt3306a_set_inversion_auto(state, 0);
833 ret = lgdt3306a_set_inversion(state, 1);
840 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
847 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
854 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
861 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
865 if (state->cfg->xtalMHz == 24) { /* 24MHz */
867 ret = lgdt3306a_read_reg(state, 0x0005, &val);
872 ret = lgdt3306a_write_reg(state, 0x0005, val);
875 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
880 ret = lgdt3306a_read_reg(state, 0x000d, &val);
885 ret = lgdt3306a_write_reg(state, 0x000d, val);
889 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
891 ret = lgdt3306a_read_reg(state, 0x0005, &val);
896 ret = lgdt3306a_write_reg(state, 0x0005, val);
899 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
904 ret = lgdt3306a_read_reg(state, 0x000d, &val);
909 ret = lgdt3306a_write_reg(state, 0x000d, val);
913 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
916 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
917 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
921 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
922 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
925 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
928 ret = lgdt3306a_read_reg(state, 0x103c, &val);
931 ret = lgdt3306a_write_reg(state, 0x103c, val);
934 ret = lgdt3306a_read_reg(state, 0x103d, &val);
937 ret = lgdt3306a_write_reg(state, 0x103d, val);
940 ret = lgdt3306a_read_reg(state, 0x1036, &val);
943 ret = lgdt3306a_write_reg(state, 0x1036, val);
946 ret = lgdt3306a_read_reg(state, 0x211f, &val);
948 ret = lgdt3306a_write_reg(state, 0x211f, val);
951 ret = lgdt3306a_read_reg(state, 0x2849, &val);
953 ret = lgdt3306a_write_reg(state, 0x2849, val);
956 ret = lgdt3306a_set_vsb(state);
959 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
962 ret = lgdt3306a_mpeg_tristate(state, 1);
965 ret = lgdt3306a_sleep(state);
978 struct lgdt3306a_state *state = fe->demodulator_priv;
983 if (state->current_frequency == p->frequency &&
984 state->current_modulation == p->modulation) {
988 state->current_frequency = -1;
989 state->current_modulation = -1;
991 ret = lgdt3306a_power(state, 1); /* power up */
1002 state->current_frequency = p->frequency;
1006 ret = lgdt3306a_set_modulation(state, p);
1010 ret = lgdt3306a_agc_setup(state, p);
1014 ret = lgdt3306a_set_if(state, p);
1020 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1024 ret = lgdt3306a_mpeg_mode_polarity(state,
1025 state->cfg->tpclk_edge,
1026 state->cfg->tpvalid_polarity);
1030 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
1034 ret = lgdt3306a_soft_reset(state);
1039 lgdt3306a_DumpAllRegs(state);
1041 state->current_frequency = p->frequency;
1049 struct lgdt3306a_state *state = fe->demodulator_priv;
1052 state->current_frequency, state->current_modulation);
1054 p->modulation = state->current_modulation;
1055 p->frequency = state->current_frequency;
1069 static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1076 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1081 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1085 ret = lgdt3306a_read_reg(state, 0x2191, &val);
1090 ret = lgdt3306a_read_reg(state, 0x2180, &val);
1095 ret = lgdt3306a_read_reg(state, 0x2181, &val);
1104 ret = lgdt3306a_read_reg(state, 0x1061, &val);
1116 ret = lgdt3306a_write_reg(state, 0x1061, val);
1121 ret = lgdt3306a_read_reg(state, 0x0024, &val);
1128 ret = lgdt3306a_write_reg(state, 0x0024, val);
1133 ret = lgdt3306a_read_reg(state, 0x103d, &val);
1138 ret = lgdt3306a_write_reg(state, 0x103d, val);
1144 lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
1149 ret = lgdt3306a_read_reg(state, 0x0081, &val);
1158 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1175 lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1188 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1202 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1216 modeOper = lgdt3306a_check_oper_mode(state);
1218 ret = lgdt3306a_read_reg(state, 0x1094, &val);
1234 modeOper = lgdt3306a_check_oper_mode(state);
1236 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1261 lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
1267 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1277 static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1284 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1289 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1295 ret = lgdt3306a_read_reg(state, 0x2199, &val);
1300 ret = lgdt3306a_read_reg(state, 0x0090, &val);
1313 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1318 ret = lgdt3306a_write_reg(state, 0x2135, val);
1322 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1327 ret = lgdt3306a_write_reg(state, 0x2141, val);
1331 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1335 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1340 ret = lgdt3306a_write_reg(state, 0x2135, val);
1344 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1349 ret = lgdt3306a_write_reg(state, 0x2141, val);
1353 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1361 lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
1369 syncLockStatus = lgdt3306a_check_lock_status(state,
1382 lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
1390 FECLockStatus = lgdt3306a_check_lock_status(state,
1403 lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
1411 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1422 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1427 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1486 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1492 mse = (read_reg(state, 0x00ec) << 8) |
1493 (read_reg(state, 0x00ed));
1494 pwr = (read_reg(state, 0x00e8) << 8) |
1495 (read_reg(state, 0x00e9));
1507 lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
1515 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1521 ret = lgdt3306a_pre_monitoring(state);
1525 packet_error = lgdt3306a_get_packet_error(state);
1526 snr = lgdt3306a_calculate_snr_x100(state);
1538 lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
1545 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
1552 packet_error = lgdt3306a_get_packet_error(state);
1553 snr = lgdt3306a_calculate_snr_x100(state);
1567 struct lgdt3306a_state *state = fe->demodulator_priv;
1581 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
1585 switch (state->current_modulation) {
1589 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
1597 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
1603 ret = lgdt3306a_monitor_vsb(state);
1613 c->cnr.stat[0].svalue = lgdt3306a_calculate_snr_x100(state) * 10;
1625 struct lgdt3306a_state *state = fe->demodulator_priv;
1627 state->snr = lgdt3306a_calculate_snr_x100(state);
1629 *snr = state->snr/10;
1640 struct lgdt3306a_state *state = fe->demodulator_priv;
1649 switch (state->current_modulation) {
1657 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1674 if (state->snr <= (ref_snr - 100))
1676 else if (state->snr <= ref_snr)
1679 str = state->snr - ref_snr;
1697 struct lgdt3306a_state *state = fe->demodulator_priv;
1704 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1705 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1706 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1707 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
1716 struct lgdt3306a_state *state = fe->demodulator_priv;
1722 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
1734 struct lgdt3306a_state *state = fe->demodulator_priv;
1739 state->current_frequency = -1; /* force re-tune */
1786 struct lgdt3306a_state *state = fe->demodulator_priv;
1789 kfree(state);
1797 struct lgdt3306a_state *state = NULL;
1805 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1806 if (state == NULL)
1809 state->cfg = config;
1810 state->i2c_adap = i2c_adap;
1812 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1814 state->frontend.demodulator_priv = state;
1819 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1829 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1839 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1850 state->current_frequency = -1;
1851 state->current_modulation = -1;
1853 lgdt3306a_sleep(state);
1855 return &state->frontend;
1859 kfree(state);
2098 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2101 lgdt3306a_DumpRegs(state);
2104 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2116 lgdt3306a_read_reg(state, regtab[i], ®val1[i]);
2159 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2161 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2167 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2169 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2175 struct lgdt3306a_state *state;
2199 state = fe->demodulator_priv;
2200 state->frontend.ops.release = NULL;
2203 state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2206 if (!state->muxc) {
2210 state->muxc->priv = client;
2211 ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2217 *config->i2c_adapter = state->muxc->adapter[0];
2225 kfree(state);
2235 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2237 i2c_mux_del_adapters(state->muxc);
2239 state->frontend.ops.release = NULL;
2240 state->frontend.demodulator_priv = NULL;
2242 kfree(state->cfg);
2243 kfree(state);