Lines Matching refs:status
228 int status;
234 status = drxk_i2c_transfer(state, &msg, 1);
235 if (status >= 0 && status != 1)
236 status = -EIO;
238 if (status < 0)
241 return status;
247 int status;
255 status = drxk_i2c_transfer(state, msgs, 2);
256 if (status != 2) {
259 if (status >= 0)
260 status = -EIO;
263 return status;
271 int status;
289 status = i2c_read(state, adr, mm1, len, mm2, 2);
290 if (status < 0)
291 return status;
305 int status;
323 status = i2c_read(state, adr, mm1, len, mm2, 4);
324 if (status < 0)
325 return status;
401 int status = 0, blk_size = block_size;
432 status = i2c_write(state, state->demod_address,
434 if (status < 0) {
443 return status;
452 int status;
458 status = i2c_read1(state, state->demod_address, &data);
459 if (status < 0) {
462 status = i2c_write(state, state->demod_address,
466 if (status < 0)
468 status = i2c_read1(state, state->demod_address,
470 } while (status < 0 &&
472 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
477 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
478 if (status < 0)
480 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
481 if (status < 0)
484 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
485 if (status < 0)
491 if (status < 0)
492 pr_err("Error %d on %s\n", status, __func__);
494 return status;
735 int status = 0;
742 status = write16(state, SCU_RAM_GPIO__A,
744 if (status < 0)
747 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
748 if (status < 0)
750 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
751 if (status < 0)
753 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
754 if (status < 0)
756 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
757 if (status < 0)
759 status = write16(state, SIO_TOP_COMM_KEY__A, key);
761 if (status < 0)
762 pr_err("Error %d on %s\n", status, __func__);
763 return status;
770 int status;
777 status = write16(state, SCU_RAM_GPIO__A,
779 if (status < 0)
781 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
782 if (status < 0)
784 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
785 if (status < 0)
787 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
788 if (status < 0)
815 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
816 if (status < 0)
819 pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
837 status = -EINVAL;
949 status = -EINVAL;
959 if (status < 0)
960 pr_err("Error %d on %s\n", status, __func__);
963 return status;
968 int status;
974 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
975 if (status < 0)
993 status = read16(state, SIO_HI_RA_RAM_CMD__A,
995 } while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));
996 if (status < 0)
998 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1001 if (status < 0)
1002 pr_err("Error %d on %s\n", status, __func__);
1004 return status;
1009 int status;
1015 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1017 if (status < 0)
1019 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1021 if (status < 0)
1023 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1025 if (status < 0)
1027 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1029 if (status < 0)
1031 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1033 if (status < 0)
1035 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1037 if (status < 0)
1039 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1040 if (status < 0)
1046 if (status < 0)
1047 pr_err("Error %d on %s\n", status, __func__);
1048 return status;
1065 int status;
1075 status = write16(state, SCU_RAM_GPIO__A,
1077 if (status < 0)
1081 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1082 if (status < 0)
1087 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1088 if (status < 0)
1090 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1091 if (status < 0)
1093 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1094 if (status < 0)
1096 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1097 if (status < 0)
1099 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1100 if (status < 0)
1102 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1103 if (status < 0)
1105 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1106 if (status < 0)
1108 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1109 if (status < 0)
1111 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1112 if (status < 0)
1114 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1115 if (status < 0)
1117 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1118 if (status < 0)
1120 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1121 if (status < 0)
1132 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1133 if (status < 0)
1139 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1140 if (status < 0)
1142 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1143 if (status < 0)
1148 status = write16(state, SIO_PDR_MD1_CFG__A,
1150 if (status < 0)
1152 status = write16(state, SIO_PDR_MD2_CFG__A,
1154 if (status < 0)
1156 status = write16(state, SIO_PDR_MD3_CFG__A,
1158 if (status < 0)
1160 status = write16(state, SIO_PDR_MD4_CFG__A,
1162 if (status < 0)
1164 status = write16(state, SIO_PDR_MD5_CFG__A,
1166 if (status < 0)
1168 status = write16(state, SIO_PDR_MD6_CFG__A,
1170 if (status < 0)
1172 status = write16(state, SIO_PDR_MD7_CFG__A,
1174 if (status < 0)
1181 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1182 if (status < 0)
1184 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1185 if (status < 0)
1187 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1188 if (status < 0)
1190 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1191 if (status < 0)
1193 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1194 if (status < 0)
1196 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1197 if (status < 0)
1199 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1200 if (status < 0)
1203 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1204 if (status < 0)
1206 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1207 if (status < 0)
1211 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1212 if (status < 0)
1215 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1217 if (status < 0)
1218 pr_err("Error %d on %s\n", status, __func__);
1219 return status;
1233 int status;
1238 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1239 if (status < 0)
1241 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1242 if (status < 0)
1244 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1245 if (status < 0)
1247 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1248 if (status < 0)
1254 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1255 if (status < 0)
1262 status = -EINVAL;
1266 if (status < 0)
1267 pr_err("Error %d on %s\n", status, __func__);
1270 return status;
1283 int status = 0;
1327 status = write_block(state, address, block_size, p_src);
1328 if (status < 0) {
1329 pr_err("Error %d while loading firmware\n", status);
1335 return status;
1340 int status;
1353 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1354 if (status >= 0 && data == desired_status) {
1355 /* tokenring already has correct status */
1356 return status;
1359 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1363 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1364 if ((status >= 0 && data == desired_status)
1373 return status;
1378 int status = 0;
1385 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1386 if (status < 0)
1389 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1390 if (status < 0)
1394 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1395 if (status < 0)
1398 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1401 if (status < 0)
1402 pr_err("Error %d on %s\n", status, __func__);
1404 return status;
1415 int status = -EINVAL;
1426 pr_err("Error %d on %s\n", status, __func__);
1427 return status;
1449 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1450 if (status < 0)
1455 status = -EIO;
1464 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1466 if (status < 0)
1495 status = -EINVAL;
1500 if (status < 0)
1501 pr_err("Error %d on %s\n", status, __func__);
1504 return status;
1510 int status;
1515 status = read16(state, IQM_AF_STDBY__A, &data);
1516 if (status < 0)
1533 status = write16(state, IQM_AF_STDBY__A, data);
1536 if (status < 0)
1537 pr_err("Error %d on %s\n", status, __func__);
1538 return status;
1543 int status = 0;
1579 status = power_up_device(state);
1580 if (status < 0)
1582 status = dvbt_enable_ofdm_token_ring(state, true);
1583 if (status < 0)
1601 status = mpegts_stop(state);
1602 if (status < 0)
1604 status = power_down_dvbt(state, false);
1605 if (status < 0)
1610 status = mpegts_stop(state);
1611 if (status < 0)
1613 status = power_down_qam(state);
1614 if (status < 0)
1620 status = dvbt_enable_ofdm_token_ring(state, false);
1621 if (status < 0)
1623 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1624 if (status < 0)
1626 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1627 if (status < 0)
1633 status = hi_cfg_command(state);
1634 if (status < 0)
1641 if (status < 0)
1642 pr_err("Error %d on %s\n", status, __func__);
1644 return status;
1652 int status;
1656 status = read16(state, SCU_COMM_EXEC__A, &data);
1657 if (status < 0)
1661 status = scu_command(state,
1665 if (status < 0)
1668 status = scu_command(state,
1672 if (status < 0)
1677 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1678 if (status < 0)
1680 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1681 if (status < 0)
1683 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1684 if (status < 0)
1688 status = set_iqm_af(state, false);
1689 if (status < 0)
1694 status = ctrl_power_mode(state, &power_mode);
1695 if (status < 0)
1699 if (status < 0)
1700 pr_err("Error %d on %s\n", status, __func__);
1701 return status;
1707 int status = 0;
1717 status = write16(state, SCU_RAM_GPIO__A,
1719 if (status < 0)
1731 status = mpegts_stop(state);
1732 if (status < 0)
1734 status = power_down_dvbt(state, true);
1735 if (status < 0)
1741 status = mpegts_stop(state);
1742 if (status < 0)
1744 status = power_down_qam(state);
1745 if (status < 0)
1751 status = -EINVAL;
1762 status = set_dvbt_standard(state, o_mode);
1763 if (status < 0)
1771 status = set_qam_standard(state, o_mode);
1772 if (status < 0)
1777 status = -EINVAL;
1780 if (status < 0)
1781 pr_err("Error %d on %s\n", status, __func__);
1782 return status;
1788 int status = -EINVAL;
1809 status = set_qam(state, i_freqk_hz, offsetk_hz);
1810 if (status < 0)
1816 status = mpegts_stop(state);
1817 if (status < 0)
1819 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1820 if (status < 0)
1822 status = dvbt_start(state);
1823 if (status < 0)
1831 if (status < 0)
1832 pr_err("Error %d on %s\n", status, __func__);
1833 return status;
1846 int status = -EINVAL;
1860 status = get_qam_lock_status(state, p_lock_status);
1863 status = get_dvbt_lock_status(state, p_lock_status);
1871 if (status < 0)
1872 pr_err("Error %d on %s\n", status, __func__);
1873 return status;
1878 int status;
1883 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1884 if (status < 0)
1887 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1888 if (status < 0)
1890 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1892 if (status < 0)
1893 pr_err("Error %d on %s\n", status, __func__);
1894 return status;
1899 int status;
1904 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1905 if (status < 0)
1907 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1908 if (status < 0)
1910 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1911 if (status < 0)
1913 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1914 if (status < 0)
1916 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1917 if (status < 0)
1919 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1920 if (status < 0)
1922 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1923 if (status < 0)
1925 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1926 if (status < 0)
1930 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1931 if (status < 0)
1933 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1934 if (status < 0)
1936 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1938 if (status < 0)
1939 pr_err("Error %d on %s\n", status, __func__);
1941 return status;
1947 int status;
1964 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1965 if (status < 0)
1967 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1968 if (status < 0)
2003 status = -EINVAL;
2005 if (status < 0)
2047 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2048 if (status < 0)
2050 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2051 if (status < 0)
2053 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2054 if (status < 0)
2056 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2057 if (status < 0)
2059 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2060 if (status < 0)
2062 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2063 if (status < 0)
2067 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2068 if (status < 0)
2070 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2072 if (status < 0)
2074 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2076 if (status < 0)
2077 pr_err("Error %d on %s\n", status, __func__);
2078 return status;
2119 int status = -EINVAL;
2131 status = read16(state, IQM_AF_STDBY__A, &data);
2132 if (status < 0)
2135 status = write16(state, IQM_AF_STDBY__A, data);
2136 if (status < 0)
2138 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2139 if (status < 0)
2150 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2151 if (status < 0)
2155 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2156 if (status < 0)
2164 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2165 if (status < 0)
2175 status = -EINVAL;
2181 status = write16(state,
2184 if (status < 0)
2189 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2191 if (status < 0)
2195 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2197 if (status < 0)
2204 status = read16(state, IQM_AF_STDBY__A, &data);
2205 if (status < 0)
2208 status = write16(state, IQM_AF_STDBY__A, data);
2209 if (status < 0)
2213 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2214 if (status < 0)
2221 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2222 if (status < 0)
2226 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2227 if (status < 0)
2231 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2233 if (status < 0)
2239 status = read16(state, IQM_AF_STDBY__A, &data);
2240 if (status < 0)
2243 status = write16(state, IQM_AF_STDBY__A, data);
2244 if (status < 0)
2248 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2249 if (status < 0)
2252 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2253 if (status < 0)
2258 status = -EINVAL;
2262 if (status < 0)
2263 pr_err("Error %d on %s\n", status, __func__);
2264 return status;
2273 int status = 0;
2282 status = read16(state, IQM_AF_STDBY__A, &data);
2283 if (status < 0)
2286 status = write16(state, IQM_AF_STDBY__A, data);
2287 if (status < 0)
2290 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2291 if (status < 0)
2302 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2303 if (status < 0)
2307 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2308 if (status < 0)
2315 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2316 if (status < 0)
2326 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2328 if (status < 0)
2335 status = read16(state, IQM_AF_STDBY__A, &data);
2336 if (status < 0)
2339 status = write16(state, IQM_AF_STDBY__A, data);
2340 if (status < 0)
2343 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2344 if (status < 0)
2355 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2356 if (status < 0)
2360 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2362 if (status < 0)
2369 status = read16(state, IQM_AF_STDBY__A, &data);
2370 if (status < 0)
2373 status = write16(state, IQM_AF_STDBY__A, data);
2374 if (status < 0)
2378 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2379 if (status < 0)
2382 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2383 if (status < 0)
2390 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2392 if (status < 0)
2393 pr_err("Error %d on %s\n", status, __func__);
2394 return status;
2400 int status = 0;
2412 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2413 if (status < 0) {
2414 pr_err("Error %d on %s\n", status, __func__);
2443 return status;
2449 int status;
2466 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2468 if (status < 0)
2470 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2472 if (status < 0)
2474 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2476 if (status < 0)
2478 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2480 if (status < 0)
2488 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
2489 if (status < 0)
2497 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2499 if (status < 0)
2545 if (status < 0)
2546 pr_err("Error %d on %s\n", status, __func__);
2547 return status;
2571 int status = 0;
2602 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2603 if (status < 0)
2605 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2607 if (status < 0)
2611 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2613 if (status < 0)
2637 int status = 0;
2647 status = get_qam_signal_to_noise(state, &signal_to_noise);
2648 if (status < 0)
2679 return status;
2714 int status = -EINVAL;
2726 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2728 if (status < 0)
2731 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2733 if (status < 0)
2736 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2738 if (status < 0)
2742 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2745 if (status < 0)
2746 pr_err("Error %d on %s\n", status, __func__);
2747 return status;
2753 int status = -EINVAL;
2761 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2763 if (status < 0)
2764 pr_err("Error %d on %s\n", status, __func__);
2765 return status;
2774 int status;
2780 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2781 if (status < 0)
2783 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2784 if (status < 0)
2786 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2787 if (status < 0)
2789 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2790 if (status < 0)
2792 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2793 if (status < 0)
2795 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2796 if (status < 0)
2801 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2802 if (status < 0)
2807 status = -EINVAL;
2811 if (status < 0)
2812 pr_err("Error %d on %s\n", status, __func__);
2815 return status;
2822 int status;
2827 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2828 if (status < 0)
2830 status = write16(state, IQM_AF_START_LOCK__A, 1);
2831 if (status < 0)
2835 status = read16(state, IQM_AF_PHASE0__A, &data);
2836 if (status < 0)
2840 status = read16(state, IQM_AF_PHASE1__A, &data);
2841 if (status < 0)
2845 status = read16(state, IQM_AF_PHASE2__A, &data);
2846 if (status < 0)
2852 if (status < 0)
2853 pr_err("Error %d on %s\n", status, __func__);
2854 return status;
2860 int status;
2864 status = adc_sync_measurement(state, &count);
2865 if (status < 0)
2872 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2873 if (status < 0)
2885 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2886 if (status < 0)
2888 status = adc_sync_measurement(state, &count);
2889 if (status < 0)
2894 status = -EINVAL;
2896 if (status < 0)
2897 pr_err("Error %d on %s\n", status, __func__);
2898 return status;
2911 int status;
2960 status = write32(state, IQM_FS_RATE_OFS_LO__A,
2962 if (status < 0)
2963 pr_err("Error %d on %s\n", status, __func__);
2964 return status;
2986 int status = 0;
3019 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3021 if (status < 0)
3024 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3025 if (status < 0)
3027 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3028 if (status < 0)
3030 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3031 if (status < 0)
3033 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3034 if (status < 0)
3036 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3038 if (status < 0)
3040 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3042 if (status < 0)
3044 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3045 if (status < 0)
3047 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3048 if (status < 0)
3050 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3051 if (status < 0)
3053 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3054 if (status < 0)
3056 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3057 if (status < 0)
3059 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3060 if (status < 0)
3063 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3065 if (status < 0)
3067 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3069 if (status < 0)
3071 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3072 if (status < 0)
3075 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3076 if (status < 0)
3078 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3079 if (status < 0)
3081 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3082 if (status < 0)
3085 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3086 if (status < 0)
3088 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3089 if (status < 0)
3091 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3092 if (status < 0)
3094 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3095 if (status < 0)
3097 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3098 if (status < 0)
3100 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3101 if (status < 0)
3103 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3104 if (status < 0)
3106 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3107 if (status < 0)
3109 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3110 if (status < 0)
3112 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3113 if (status < 0)
3115 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3116 if (status < 0)
3118 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3119 if (status < 0)
3121 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3122 if (status < 0)
3124 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3125 if (status < 0)
3127 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3128 if (status < 0)
3130 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3131 if (status < 0)
3133 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3134 if (status < 0)
3136 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3137 if (status < 0)
3139 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3140 if (status < 0)
3144 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3145 if (status < 0)
3154 status = write16(state, SCU_RAM_AGC_KI__A, data);
3156 if (status < 0)
3157 pr_err("Error %d on %s\n", status, __func__);
3158 return status;
3163 int status;
3167 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3169 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3171 if (status < 0)
3172 pr_err("Error %d on %s\n", status, __func__);
3173 return status;
3185 int status;
3188 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3191 status = -EINVAL;
3193 if (status < 0)
3200 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3203 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3212 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3213 if (status < 0)
3222 status = 0;
3231 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3235 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3240 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3244 status = -EINVAL;
3246 if (status < 0)
3253 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3256 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3260 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3263 status = -EINVAL;
3265 if (status < 0)
3277 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3289 status = -EINVAL;
3293 if (status < 0)
3294 pr_err("Error %d on %s\n", status, __func__);
3295 return status;
3301 int status;
3304 status = ctrl_power_mode(state, &power_mode);
3305 if (status < 0)
3306 pr_err("Error %d on %s\n", status, __func__);
3307 return status;
3312 int status;
3316 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3318 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3319 if (status < 0)
3320 pr_err("Error %d on %s\n", status, __func__);
3321 return status;
3328 int status;
3333 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3337 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3339 if (status < 0)
3340 pr_err("Error %d on %s\n", status, __func__);
3342 return status;
3349 int status;
3352 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3353 if (status < 0)
3373 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3375 if (status < 0)
3376 pr_err("Error %d on %s\n", status, __func__);
3377 return status;
3383 int status = -EINVAL;
3395 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3398 if (status < 0)
3399 pr_err("Error %d on %s\n", status, __func__);
3400 return status;
3415 int status;
3423 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3424 if (status < 0)
3426 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3427 if (status < 0)
3429 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3430 if (status < 0)
3432 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3433 if (status < 0)
3435 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3438 if (status < 0)
3439 pr_err("Error %d on %s\n", status, __func__);
3440 return status;
3458 int status;
3466 status = scu_command(state,
3470 if (status < 0)
3474 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3477 if (status < 0)
3481 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3482 if (status < 0)
3484 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3485 if (status < 0)
3487 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3488 if (status < 0)
3493 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3494 if (status < 0)
3497 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3498 if (status < 0)
3501 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3502 if (status < 0)
3505 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3506 if (status < 0)
3508 status = set_iqm_af(state, true);
3509 if (status < 0)
3512 status = write16(state, IQM_AF_AGC_RF__A, 0);
3513 if (status < 0)
3517 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3518 if (status < 0)
3520 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3521 if (status < 0)
3523 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3524 if (status < 0)
3527 status = write16(state, IQM_RC_STRETCH__A, 16);
3528 if (status < 0)
3530 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3531 if (status < 0)
3533 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3534 if (status < 0)
3536 status = write16(state, IQM_CF_SCALE__A, 1600);
3537 if (status < 0)
3539 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3540 if (status < 0)
3544 status = write16(state, IQM_AF_CLP_TH__A, 448);
3545 if (status < 0)
3547 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3548 if (status < 0)
3551 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3553 if (status < 0)
3556 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3557 if (status < 0)
3559 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3560 if (status < 0)
3563 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3564 if (status < 0)
3566 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3567 if (status < 0)
3571 status = adc_synchronization(state);
3572 if (status < 0)
3574 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3575 if (status < 0)
3579 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3580 if (status < 0)
3583 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3584 if (status < 0)
3586 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3587 if (status < 0)
3591 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3592 if (status < 0)
3595 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3596 if (status < 0)
3600 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3601 if (status < 0)
3606 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3608 if (status < 0)
3614 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3615 if (status < 0)
3617 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3618 if (status < 0)
3623 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3624 if (status < 0)
3629 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3630 if (status < 0)
3633 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3634 if (status < 0)
3637 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3638 if (status < 0)
3642 status = mpegts_dto_setup(state, OM_DVBT);
3643 if (status < 0)
3646 status = dvbt_activate_presets(state);
3647 if (status < 0)
3651 if (status < 0)
3652 pr_err("Error %d on %s\n", status, __func__);
3653 return status;
3665 int status;
3672 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3675 if (status < 0)
3678 status = mpegts_start(state);
3679 if (status < 0)
3681 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3682 if (status < 0)
3685 if (status < 0)
3686 pr_err("Error %d on %s\n", status, __func__);
3687 return status;
3707 int status;
3712 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3715 if (status < 0)
3719 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3720 if (status < 0)
3724 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3725 if (status < 0)
3727 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3728 if (status < 0)
3733 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3734 if (status < 0)
3816 status = -EINVAL;
3822 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3823 if (status < 0)
3867 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3869 if (status < 0)
3872 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3874 if (status < 0)
3876 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3878 if (status < 0)
3880 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3882 if (status < 0)
3884 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3886 if (status < 0)
3891 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3893 if (status < 0)
3896 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3898 if (status < 0)
3900 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3902 if (status < 0)
3904 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3906 if (status < 0)
3908 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3910 if (status < 0)
3915 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3917 if (status < 0)
3920 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3922 if (status < 0)
3924 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3926 if (status < 0)
3928 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3930 if (status < 0)
3932 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3934 if (status < 0)
3938 status = -EINVAL;
3969 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
3970 if (status < 0)
3976 status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
3977 if (status < 0)
3980 status = set_frequency_shifter(state, intermediate_freqk_hz,
3982 if (status < 0)
3988 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3989 if (status < 0)
3993 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
3994 if (status < 0)
3996 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
3997 if (status < 0)
4001 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4004 if (status < 0)
4013 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4015 if (status < 0)
4019 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4021 if (status < 0)
4022 pr_err("Error %d on %s\n", status, __func__);
4024 return status;
4031 * \brief Retrieve lock status .
4033 * \param lockStat Pointer to lock status structure.
4039 int status;
4053 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4054 if (status < 0)
4059 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4060 if (status < 0)
4072 if (status < 0)
4073 pr_err("Error %d on %s\n", status, __func__);
4075 return status;
4081 int status;
4084 status = ctrl_power_mode(state, &power_mode);
4085 if (status < 0)
4086 pr_err("Error %d on %s\n", status, __func__);
4088 return status;
4097 int status = 0;
4100 status = read16(state, SCU_COMM_EXEC__A, &data);
4101 if (status < 0)
4109 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4110 if (status < 0)
4112 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4115 if (status < 0)
4119 status = set_iqm_af(state, false);
4122 if (status < 0)
4123 pr_err("Error %d on %s\n", status, __func__);
4125 return status;
4149 int status = 0;
4177 status = -EINVAL;
4179 if (status < 0)
4193 status = -EINVAL;
4194 if (status < 0)
4202 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4203 if (status < 0)
4205 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4207 if (status < 0)
4209 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4211 if (status < 0)
4212 pr_err("Error %d on %s\n", status, __func__);
4213 return status;
4218 int status = 0;
4223 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4224 if (status < 0)
4226 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4227 if (status < 0)
4229 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4230 if (status < 0)
4232 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4233 if (status < 0)
4235 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4236 if (status < 0)
4238 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4239 if (status < 0)
4242 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4243 if (status < 0)
4245 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4246 if (status < 0)
4248 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4249 if (status < 0)
4251 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4252 if (status < 0)
4254 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4255 if (status < 0)
4257 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4258 if (status < 0)
4261 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4262 if (status < 0)
4264 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4265 if (status < 0)
4267 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4268 if (status < 0)
4272 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4274 if (status < 0)
4278 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4279 if (status < 0)
4281 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4282 if (status < 0)
4284 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4285 if (status < 0)
4287 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4288 if (status < 0)
4290 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4291 if (status < 0)
4293 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4294 if (status < 0)
4296 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4297 if (status < 0)
4299 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4300 if (status < 0)
4303 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4304 if (status < 0)
4306 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4307 if (status < 0)
4309 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4310 if (status < 0)
4312 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4313 if (status < 0)
4315 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4316 if (status < 0)
4318 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4319 if (status < 0)
4321 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4322 if (status < 0)
4324 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4325 if (status < 0)
4327 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4328 if (status < 0)
4330 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4331 if (status < 0)
4333 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4334 if (status < 0)
4336 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4337 if (status < 0)
4343 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4344 if (status < 0)
4346 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4347 if (status < 0)
4349 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4350 if (status < 0)
4352 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4353 if (status < 0)
4355 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4356 if (status < 0)
4358 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4359 if (status < 0)
4362 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4363 if (status < 0)
4365 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4366 if (status < 0)
4368 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4369 if (status < 0)
4375 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4376 if (status < 0)
4378 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4379 if (status < 0)
4381 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4382 if (status < 0)
4384 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4385 if (status < 0)
4387 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4388 if (status < 0)
4390 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4391 if (status < 0)
4393 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4394 if (status < 0)
4398 if (status < 0)
4399 pr_err("Error %d on %s\n", status, __func__);
4400 return status;
4412 int status = 0;
4418 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4419 if (status < 0)
4421 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4422 if (status < 0)
4424 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4425 if (status < 0)
4427 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4428 if (status < 0)
4430 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4431 if (status < 0)
4433 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4434 if (status < 0)
4438 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4439 if (status < 0)
4441 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4442 if (status < 0)
4444 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4445 if (status < 0)
4447 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4448 if (status < 0)
4450 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4451 if (status < 0)
4453 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4454 if (status < 0)
4457 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4458 if (status < 0)
4460 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4461 if (status < 0)
4463 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4464 if (status < 0)
4469 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4471 if (status < 0)
4477 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4478 if (status < 0)
4480 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4481 if (status < 0)
4483 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4484 if (status < 0)
4486 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4487 if (status < 0)
4489 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4490 if (status < 0)
4492 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4493 if (status < 0)
4495 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4496 if (status < 0)
4498 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4499 if (status < 0)
4502 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4503 if (status < 0)
4505 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4506 if (status < 0)
4508 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4509 if (status < 0)
4511 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4512 if (status < 0)
4514 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4515 if (status < 0)
4517 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4518 if (status < 0)
4520 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4521 if (status < 0)
4523 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4524 if (status < 0)
4526 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4527 if (status < 0)
4529 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4530 if (status < 0)
4532 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4533 if (status < 0)
4535 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4536 if (status < 0)
4542 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4543 if (status < 0)
4545 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4546 if (status < 0)
4548 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4549 if (status < 0)
4551 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4552 if (status < 0)
4554 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4555 if (status < 0)
4557 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4558 if (status < 0)
4561 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4562 if (status < 0)
4564 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4565 if (status < 0)
4567 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4568 if (status < 0)
4574 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4575 if (status < 0)
4577 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4578 if (status < 0)
4580 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4581 if (status < 0)
4583 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4584 if (status < 0)
4586 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4587 if (status < 0)
4589 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4590 if (status < 0)
4592 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4594 if (status < 0)
4595 pr_err("Error %d on %s\n", status, __func__);
4596 return status;
4608 int status = 0;
4613 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4614 if (status < 0)
4616 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4617 if (status < 0)
4619 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4620 if (status < 0)
4622 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4623 if (status < 0)
4625 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4626 if (status < 0)
4628 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4629 if (status < 0)
4633 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4634 if (status < 0)
4636 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4637 if (status < 0)
4639 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4640 if (status < 0)
4642 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4643 if (status < 0)
4645 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4646 if (status < 0)
4648 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4649 if (status < 0)
4652 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4653 if (status < 0)
4655 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4656 if (status < 0)
4658 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4659 if (status < 0)
4663 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4665 if (status < 0)
4671 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4672 if (status < 0)
4674 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4675 if (status < 0)
4677 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4678 if (status < 0)
4680 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4681 if (status < 0)
4683 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4684 if (status < 0)
4686 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4687 if (status < 0)
4689 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4690 if (status < 0)
4692 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4693 if (status < 0)
4696 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4697 if (status < 0)
4699 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4700 if (status < 0)
4702 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4703 if (status < 0)
4705 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4706 if (status < 0)
4708 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4709 if (status < 0)
4711 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4712 if (status < 0)
4714 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4715 if (status < 0)
4717 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4718 if (status < 0)
4720 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4721 if (status < 0)
4723 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4724 if (status < 0)
4726 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4727 if (status < 0)
4729 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4730 if (status < 0)
4736 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4737 if (status < 0)
4739 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4740 if (status < 0)
4742 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4743 if (status < 0)
4745 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4746 if (status < 0)
4748 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4749 if (status < 0)
4751 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4752 if (status < 0)
4755 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4756 if (status < 0)
4758 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4759 if (status < 0)
4761 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4762 if (status < 0)
4768 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4769 if (status < 0)
4771 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4772 if (status < 0)
4774 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4775 if (status < 0)
4777 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4778 if (status < 0)
4780 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4781 if (status < 0)
4783 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4784 if (status < 0)
4786 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4788 if (status < 0)
4789 pr_err("Error %d on %s\n", status, __func__);
4791 return status;
4803 int status = 0;
4808 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4809 if (status < 0)
4811 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4812 if (status < 0)
4814 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4815 if (status < 0)
4817 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4818 if (status < 0)
4820 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4821 if (status < 0)
4823 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4824 if (status < 0)
4828 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4829 if (status < 0)
4831 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4832 if (status < 0)
4834 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4835 if (status < 0)
4837 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4838 if (status < 0)
4840 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4841 if (status < 0)
4843 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4844 if (status < 0)
4847 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4848 if (status < 0)
4850 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4851 if (status < 0)
4853 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4854 if (status < 0)
4860 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4862 if (status < 0)
4868 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4869 if (status < 0)
4871 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4872 if (status < 0)
4874 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4875 if (status < 0)
4877 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4878 if (status < 0)
4880 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4881 if (status < 0)
4883 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4884 if (status < 0)
4886 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4887 if (status < 0)
4889 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4890 if (status < 0)
4893 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4894 if (status < 0)
4896 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4897 if (status < 0)
4899 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4900 if (status < 0)
4902 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4903 if (status < 0)
4905 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4906 if (status < 0)
4908 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4909 if (status < 0)
4911 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4912 if (status < 0)
4914 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4915 if (status < 0)
4917 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4918 if (status < 0)
4920 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4921 if (status < 0)
4923 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4924 if (status < 0)
4926 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4927 if (status < 0)
4933 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4934 if (status < 0)
4936 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4937 if (status < 0)
4939 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4940 if (status < 0)
4942 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4943 if (status < 0)
4945 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4946 if (status < 0)
4948 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4949 if (status < 0)
4952 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4953 if (status < 0)
4955 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4956 if (status < 0)
4959 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4960 if (status < 0)
4965 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4966 if (status < 0)
4968 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
4969 if (status < 0)
4971 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
4972 if (status < 0)
4974 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
4975 if (status < 0)
4977 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
4978 if (status < 0)
4980 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
4981 if (status < 0)
4983 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
4985 if (status < 0)
4986 pr_err("Error %d on %s\n", status, __func__);
4988 return status;
5000 int status = 0;
5005 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5006 if (status < 0)
5008 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5009 if (status < 0)
5011 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5012 if (status < 0)
5014 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5015 if (status < 0)
5017 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5018 if (status < 0)
5020 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5021 if (status < 0)
5025 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5026 if (status < 0)
5028 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5029 if (status < 0)
5031 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5032 if (status < 0)
5034 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5035 if (status < 0)
5037 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5038 if (status < 0)
5040 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5041 if (status < 0)
5044 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5045 if (status < 0)
5047 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5048 if (status < 0)
5050 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5051 if (status < 0)
5056 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5058 if (status < 0)
5064 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5065 if (status < 0)
5067 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5068 if (status < 0)
5070 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5071 if (status < 0)
5073 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5074 if (status < 0)
5076 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5077 if (status < 0)
5079 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5080 if (status < 0)
5082 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5083 if (status < 0)
5085 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5086 if (status < 0)
5089 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5090 if (status < 0)
5092 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5093 if (status < 0)
5095 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5096 if (status < 0)
5098 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5099 if (status < 0)
5101 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5102 if (status < 0)
5104 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5105 if (status < 0)
5107 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5108 if (status < 0)
5110 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5111 if (status < 0)
5113 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5114 if (status < 0)
5116 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5117 if (status < 0)
5119 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5120 if (status < 0)
5122 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5123 if (status < 0)
5129 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5130 if (status < 0)
5132 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5133 if (status < 0)
5135 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5136 if (status < 0)
5138 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5139 if (status < 0)
5141 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5142 if (status < 0)
5144 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5145 if (status < 0)
5148 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5149 if (status < 0)
5151 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5152 if (status < 0)
5154 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5155 if (status < 0)
5161 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5162 if (status < 0)
5164 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5165 if (status < 0)
5167 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5168 if (status < 0)
5170 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5171 if (status < 0)
5173 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5174 if (status < 0)
5176 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5177 if (status < 0)
5179 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5181 if (status < 0)
5182 pr_err("Error %d on %s\n", status, __func__);
5183 return status;
5196 int status;
5201 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5202 if (status < 0)
5205 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5209 if (status < 0)
5210 pr_err("Error %d on %s\n", status, __func__);
5211 return status;
5229 int status;
5241 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5242 if (status < 0)
5251 status = -EINVAL;
5257 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5258 if (status < 0)
5267 status = -EINVAL;
5275 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5278 if (status < 0)
5279 pr_err("Error %d on %s\n", status, __func__);
5280 return status;
5286 * \brief Get QAM lock status.
5294 int status;
5299 status = scu_command(state,
5303 if (status < 0)
5304 pr_err("Error %d on %s\n", status, __func__);
5323 return status;
5336 int status;
5351 status = scu_command(state,
5355 if (status < 0)
5358 status = scu_command(state,
5374 status = scu_command(state,
5382 status = -EINVAL;
5386 if (status < 0)
5387 pr_warn("Warning %d on %s\n", status, __func__);
5388 return status;
5394 int status;
5405 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5406 if (status < 0)
5408 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5409 if (status < 0)
5411 status = qam_reset_qam(state);
5412 if (status < 0)
5420 status = qam_set_symbolrate(state);
5421 if (status < 0)
5443 status = -EINVAL;
5446 if (status < 0)
5454 status = qam_demodulator_command(state, qam_demod_param_count);
5461 || (!state->qam_demod_parameter_count && status < 0)) {
5463 status = qam_demodulator_command(state, qam_demod_param_count);
5466 if (status < 0) {
5490 status = set_frequency(channel, tuner_freq_offset));
5491 if (status < 0)
5494 status = set_frequency_shifter(state, intermediate_freqk_hz,
5496 if (status < 0)
5500 status = set_qam_measurement(state, state->m_constellation,
5502 if (status < 0)
5506 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5507 if (status < 0)
5509 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5510 if (status < 0)
5514 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5515 if (status < 0)
5517 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5518 if (status < 0)
5520 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5521 if (status < 0)
5523 status = write16(state, QAM_LC_MODE__A, 7);
5524 if (status < 0)
5527 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5528 if (status < 0)
5530 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5531 if (status < 0)
5533 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5534 if (status < 0)
5536 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5537 if (status < 0)
5539 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5540 if (status < 0)
5542 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5543 if (status < 0)
5545 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5546 if (status < 0)
5548 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5549 if (status < 0)
5551 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5552 if (status < 0)
5554 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5555 if (status < 0)
5557 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5558 if (status < 0)
5560 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5561 if (status < 0)
5563 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5564 if (status < 0)
5566 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5567 if (status < 0)
5569 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5570 if (status < 0)
5574 status = write16(state, QAM_SY_SP_INV__A,
5576 if (status < 0)
5580 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5581 if (status < 0)
5587 status = set_qam16(state);
5590 status = set_qam32(state);
5594 status = set_qam64(state);
5597 status = set_qam128(state);
5600 status = set_qam256(state);
5603 status = -EINVAL;
5606 if (status < 0)
5610 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5611 if (status < 0)
5617 status = mpegts_dto_setup(state, state->m_operation_mode);
5618 if (status < 0)
5622 status = mpegts_start(state);
5623 if (status < 0)
5625 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5626 if (status < 0)
5628 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5629 if (status < 0)
5631 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5632 if (status < 0)
5636 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5639 if (status < 0)
5646 if (status < 0)
5647 pr_err("Error %d on %s\n", status, __func__);
5648 return status;
5654 int status;
5667 status = power_up_qam(state);
5668 if (status < 0)
5671 status = qam_reset_qam(state);
5672 if (status < 0)
5677 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5678 if (status < 0)
5680 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5681 if (status < 0)
5688 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5693 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5697 if (status < 0)
5699 status = bl_direct_cmd(state,
5706 status = -EINVAL;
5708 if (status < 0)
5711 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5712 if (status < 0)
5714 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5715 if (status < 0)
5717 status = write16(state, IQM_CF_MIDTAP__A,
5719 if (status < 0)
5722 status = write16(state, IQM_RC_STRETCH__A, 21);
5723 if (status < 0)
5725 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5726 if (status < 0)
5728 status = write16(state, IQM_AF_CLP_TH__A, 448);
5729 if (status < 0)
5731 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5732 if (status < 0)
5734 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5735 if (status < 0)
5738 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5739 if (status < 0)
5741 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5742 if (status < 0)
5744 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5745 if (status < 0)
5747 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5748 if (status < 0)
5752 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5753 if (status < 0)
5755 status = write16(state, IQM_CF_DATATH__A, 1000);
5756 if (status < 0)
5758 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5759 if (status < 0)
5761 status = write16(state, IQM_CF_DET_LCT__A, 0);
5762 if (status < 0)
5764 status = write16(state, IQM_CF_WND_LEN__A, 1);
5765 if (status < 0)
5767 status = write16(state, IQM_CF_PKDTH__A, 1);
5768 if (status < 0)
5770 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5771 if (status < 0)
5775 status = set_iqm_af(state, true);
5776 if (status < 0)
5778 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5779 if (status < 0)
5783 status = adc_synchronization(state);
5784 if (status < 0)
5788 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5789 if (status < 0)
5793 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5794 if (status < 0)
5800 status = init_agc(state, true);
5801 if (status < 0)
5803 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5804 if (status < 0)
5808 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5809 if (status < 0)
5811 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5812 if (status < 0)
5816 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5818 if (status < 0)
5819 pr_err("Error %d on %s\n", status, __func__);
5820 return status;
5825 int status;
5830 status = write16(state, SCU_RAM_GPIO__A,
5832 if (status < 0)
5836 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5837 if (status < 0)
5843 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5845 if (status < 0)
5849 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5850 if (status < 0)
5857 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5858 if (status < 0)
5863 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5865 if (status < 0)
5869 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5870 if (status < 0)
5877 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5878 if (status < 0)
5883 status = write16(state, SIO_PDR_GPIO_CFG__A,
5885 if (status < 0)
5889 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5890 if (status < 0)
5897 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5898 if (status < 0)
5903 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5905 if (status < 0)
5906 pr_err("Error %d on %s\n", status, __func__);
5907 return status;
5912 int status = 0;
5928 status = write_gpio(state);
5930 if (status < 0)
5931 pr_err("Error %d on %s\n", status, __func__);
5932 return status;
5937 int status = 0;
5953 status = write_gpio(state);
5955 if (status < 0)
5956 pr_err("Error %d on %s\n", status, __func__);
5957 return status;
5969 int status;
5974 status = ConfigureI2CBridge(state, true);
5975 if (status < 0)
5979 status = dvbt_enable_ofdm_token_ring(state, false);
5980 if (status < 0)
5983 status = write16(state, SIO_CC_PWD_MODE__A,
5985 if (status < 0)
5987 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5988 if (status < 0)
5991 status = hi_cfg_command(state);
5993 if (status < 0)
5994 pr_err("Error %d on %s\n", status, __func__);
5996 return status;
6001 int status = 0, n = 0;
6008 status = power_up_device(state);
6009 if (status < 0)
6011 status = drxx_open(state);
6012 if (status < 0)
6015 status = write16(state, SIO_CC_SOFT_RST__A,
6019 if (status < 0)
6021 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6022 if (status < 0)
6030 status = get_device_capabilities(state);
6031 if (status < 0)
6051 status = init_hi(state);
6052 if (status < 0)
6060 status = write16(state, SCU_RAM_GPIO__A,
6062 if (status < 0)
6067 status = mpegts_disable(state);
6068 if (status < 0)
6072 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6073 if (status < 0)
6075 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6076 if (status < 0)
6080 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6082 if (status < 0)
6086 status = write16(state, SIO_BL_COMM_EXEC__A,
6088 if (status < 0)
6090 status = bl_chain_cmd(state, 0, 6, 100);
6091 if (status < 0)
6095 status = download_microcode(state, state->fw->data,
6097 if (status < 0)
6102 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6104 if (status < 0)
6108 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6109 if (status < 0)
6111 status = drxx_open(state);
6112 if (status < 0)
6118 status = ctrl_power_mode(state, &power_mode);
6119 if (status < 0)
6133 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6135 if (status < 0)
6142 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6144 if (status < 0)
6162 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6163 if (status < 0)
6168 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6169 if (status < 0)
6172 status = mpegts_dto_init(state);
6173 if (status < 0)
6175 status = mpegts_stop(state);
6176 if (status < 0)
6178 status = mpegts_configure_polarity(state);
6179 if (status < 0)
6181 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6182 if (status < 0)
6185 status = write_gpio(state);
6186 if (status < 0)
6192 status = power_down_device(state);
6193 if (status < 0)
6215 if (status < 0) {
6218 pr_err("Error %d on %s\n", status, __func__);
6221 return status;
6364 int status;
6390 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6391 if (status < 0)
6392 return status;
6395 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6396 if (status < 0)
6397 return status;
6423 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6425 if (status < 0)
6426 return status;
6428 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6430 if (status < 0)
6431 return status;
6467 int status;
6484 /* get status */
6530 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6531 if (status < 0)
6535 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6536 if (status < 0)
6541 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6542 if (status < 0)
6546 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6547 if (status < 0)
6551 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6552 if (status < 0)
6556 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6557 if (status < 0)
6583 return status;
6587 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
6598 *status = state->fe_status;
6723 int status;
6780 status = request_firmware(&fw, state->microcode_name,
6782 if (status < 0)