Lines Matching refs:rc
1376 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1421 int rc;
1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
1485 if (rc == 0)
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
1495 } while (datasize && rc == 0);
1497 return rc;
1524 int rc;
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1531 return rc;
1557 int rc;
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1566 return rc;
1767 int rc = -EIO;
1773 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
1774 if (rc == 0)
1775 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
1778 return rc;
1840 int rc;
1846 rc = drxdap_fasi_write_reg16(dev_addr,
1850 if (rc == 0) {
1852 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
1855 if (rc == 0) {
1857 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
1860 if (rc == 0) {
1862 rc = drxdap_fasi_write_reg16(dev_addr,
1867 return rc;
2108 int rc;
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy);
2146 if (rc != 0) {
2147 pr_err("error %d\n", rc);
2154 rc = drxj_dap_read_reg16(dev_addr,
2157 if (rc) {
2158 pr_err("error %d\n", rc);
2169 return rc;
2185 int rc;
2191 rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
2194 if (rc < 0)
2207 return rc;
2238 int rc;
2250 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2251 if (rc != 0) {
2252 pr_err("error %d\n", rc);
2262 return rc;
2282 int rc;
2289 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2290 if (rc != 0) {
2291 pr_err("error %d\n", rc);
2294 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2295 if (rc != 0) {
2296 pr_err("error %d\n", rc);
2299 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2300 if (rc != 0) {
2301 pr_err("error %d\n", rc);
2304 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2305 if (rc != 0) {
2306 pr_err("error %d\n", rc);
2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2312 if (rc != 0) {
2313 pr_err("error %d\n", rc);
2316 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2317 if (rc != 0) {
2318 pr_err("error %d\n", rc);
2331 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2332 if (rc != 0) {
2333 pr_err("error %d\n", rc);
2350 rc = -ETIMEDOUT;
2355 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
2356 if (rc != 0) {
2357 pr_err("error %d\n", rc);
2363 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
2364 if (rc != 0) {
2365 pr_err("error %d\n", rc);
2373 return rc;
2394 int rc;
2401 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
2402 if (rc != 0) {
2403 pr_err("error %d\n", rc);
2435 rc = hi_cfg_command(demod);
2436 if (rc != 0) {
2437 pr_err("error %d\n", rc);
2444 return rc;
2481 int rc;
2487 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2488 if (rc != 0) {
2489 pr_err("error %d\n", rc);
2492 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
2493 if (rc != 0) {
2494 pr_err("error %d\n", rc);
2497 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2498 if (rc != 0) {
2499 pr_err("error %d\n", rc);
2527 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
2528 if (rc != 0) {
2529 pr_err("error %d\n", rc);
2536 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2537 if (rc != 0) {
2538 pr_err("error %d\n", rc);
2541 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
2542 if (rc != 0) {
2543 pr_err("error %d\n", rc);
2547 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2548 if (rc != 0) {
2549 pr_err("error %d\n", rc);
2660 return rc;
2733 int rc;
2769 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
2770 if (rc != 0) {
2771 pr_err("error %d\n", rc);
2776 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
2777 if (rc != 0) {
2778 pr_err("error %d\n", rc);
2781 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
2782 if (rc != 0) {
2783 pr_err("error %d\n", rc);
2786 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
2787 if (rc != 0) {
2788 pr_err("error %d\n", rc);
2791 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
2792 if (rc != 0) {
2793 pr_err("error %d\n", rc);
2796 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
2797 if (rc != 0) {
2798 pr_err("error %d\n", rc);
2801 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
2802 if (rc != 0) {
2803 pr_err("error %d\n", rc);
2807 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
2808 if (rc != 0) {
2809 pr_err("error %d\n", rc);
2813 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
2814 if (rc != 0) {
2815 pr_err("error %d\n", rc);
2846 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2847 if (rc != 0) {
2848 pr_err("error %d\n", rc);
2851 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2852 if (rc != 0) {
2853 pr_err("error %d\n", rc);
2856 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
2857 if (rc != 0) {
2858 pr_err("error %d\n", rc);
2861 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
2862 if (rc != 0) {
2863 pr_err("error %d\n", rc);
2866 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
2867 if (rc != 0) {
2868 pr_err("error %d\n", rc);
2872 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
2873 if (rc != 0) {
2874 pr_err("error %d\n", rc);
2878 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
2879 if (rc != 0) {
2880 pr_err("error %d\n", rc);
2884 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
2885 if (rc != 0) {
2886 pr_err("error %d\n", rc);
2889 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
2890 if (rc != 0) {
2891 pr_err("error %d\n", rc);
2900 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
2901 if (rc != 0) {
2902 pr_err("error %d\n", rc);
2905 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
2906 if (rc != 0) {
2907 pr_err("error %d\n", rc);
3062 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
3063 if (rc != 0) {
3064 pr_err("error %d\n", rc);
3067 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
3068 if (rc != 0) {
3069 pr_err("error %d\n", rc);
3072 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
3073 if (rc != 0) {
3074 pr_err("error %d\n", rc);
3077 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
3078 if (rc != 0) {
3079 pr_err("error %d\n", rc);
3082 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
3083 if (rc != 0) {
3084 pr_err("error %d\n", rc);
3089 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
3090 if (rc != 0) {
3091 pr_err("error %d\n", rc);
3096 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
3097 if (rc != 0) {
3098 pr_err("error %d\n", rc);
3101 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
3102 if (rc != 0) {
3103 pr_err("error %d\n", rc);
3108 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
3109 if (rc != 0) {
3110 pr_err("error %d\n", rc);
3115 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
3116 if (rc != 0) {
3117 pr_err("error %d\n", rc);
3120 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
3121 if (rc != 0) {
3122 pr_err("error %d\n", rc);
3125 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
3126 if (rc != 0) {
3127 pr_err("error %d\n", rc);
3133 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3134 if (rc != 0) {
3135 pr_err("error %d\n", rc);
3139 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
3140 if (rc != 0) {
3141 pr_err("error %d\n", rc);
3144 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
3145 if (rc != 0) {
3146 pr_err("error %d\n", rc);
3149 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
3150 if (rc != 0) {
3151 pr_err("error %d\n", rc);
3154 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
3155 if (rc != 0) {
3156 pr_err("error %d\n", rc);
3162 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3163 if (rc != 0) {
3164 pr_err("error %d\n", rc);
3172 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3173 if (rc != 0) {
3174 pr_err("error %d\n", rc);
3177 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
3178 if (rc != 0) {
3179 pr_err("error %d\n", rc);
3182 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
3183 if (rc != 0) {
3184 pr_err("error %d\n", rc);
3187 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
3188 if (rc != 0) {
3189 pr_err("error %d\n", rc);
3192 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
3193 if (rc != 0) {
3194 pr_err("error %d\n", rc);
3197 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
3198 if (rc != 0) {
3199 pr_err("error %d\n", rc);
3202 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
3203 if (rc != 0) {
3204 pr_err("error %d\n", rc);
3207 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
3208 if (rc != 0) {
3209 pr_err("error %d\n", rc);
3213 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3214 if (rc != 0) {
3215 pr_err("error %d\n", rc);
3218 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3219 if (rc != 0) {
3220 pr_err("error %d\n", rc);
3223 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3224 if (rc != 0) {
3225 pr_err("error %d\n", rc);
3228 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3229 if (rc != 0) {
3230 pr_err("error %d\n", rc);
3233 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3234 if (rc != 0) {
3235 pr_err("error %d\n", rc);
3238 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3239 if (rc != 0) {
3240 pr_err("error %d\n", rc);
3243 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3244 if (rc != 0) {
3245 pr_err("error %d\n", rc);
3250 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3251 if (rc != 0) {
3252 pr_err("error %d\n", rc);
3256 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3257 if (rc != 0) {
3258 pr_err("error %d\n", rc);
3263 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3264 if (rc != 0) {
3265 pr_err("error %d\n", rc);
3269 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
3270 if (rc != 0) {
3271 pr_err("error %d\n", rc);
3274 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
3275 if (rc != 0) {
3276 pr_err("error %d\n", rc);
3279 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
3280 if (rc != 0) {
3281 pr_err("error %d\n", rc);
3284 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
3285 if (rc != 0) {
3286 pr_err("error %d\n", rc);
3289 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
3290 if (rc != 0) {
3291 pr_err("error %d\n", rc);
3294 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3295 if (rc != 0) {
3296 pr_err("error %d\n", rc);
3299 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3300 if (rc != 0) {
3301 pr_err("error %d\n", rc);
3304 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3305 if (rc != 0) {
3306 pr_err("error %d\n", rc);
3309 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3310 if (rc != 0) {
3311 pr_err("error %d\n", rc);
3314 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3315 if (rc != 0) {
3316 pr_err("error %d\n", rc);
3319 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3320 if (rc != 0) {
3321 pr_err("error %d\n", rc);
3324 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3325 if (rc != 0) {
3326 pr_err("error %d\n", rc);
3330 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3331 if (rc != 0) {
3332 pr_err("error %d\n", rc);
3336 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3337 if (rc != 0) {
3338 pr_err("error %d\n", rc);
3348 return rc;
3375 int rc;
3383 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
3384 if (rc != 0) {
3385 pr_err("error %d\n", rc);
3388 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
3389 if (rc != 0) {
3390 pr_err("error %d\n", rc);
3393 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
3394 if (rc != 0) {
3395 pr_err("error %d\n", rc);
3413 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
3414 if (rc != 0) {
3415 pr_err("error %d\n", rc);
3418 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
3419 if (rc != 0) {
3420 pr_err("error %d\n", rc);
3423 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
3424 if (rc != 0) {
3425 pr_err("error %d\n", rc);
3431 return rc;
3448 int rc;
3454 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
3455 if (rc != 0) {
3456 pr_err("error %d\n", rc);
3466 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
3467 if (rc != 0) {
3468 pr_err("error %d\n", rc);
3474 return rc;
3492 int rc;
3501 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
3502 if (rc != 0) {
3503 pr_err("error %d\n", rc);
3509 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
3510 if (rc != 0) {
3511 pr_err("error %d\n", rc);
3518 return rc;
3538 int rc;
3546 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3547 if (rc != 0) {
3548 pr_err("error %d\n", rc);
3566 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3567 if (rc != 0) {
3568 pr_err("error %d\n", rc);
3589 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3590 if (rc != 0) {
3591 pr_err("error %d\n", rc);
3612 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3613 if (rc != 0) {
3614 pr_err("error %d\n", rc);
3633 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3634 if (rc != 0) {
3635 pr_err("error %d\n", rc);
3651 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3652 if (rc != 0) {
3653 pr_err("error %d\n", rc);
3659 return rc;
3673 int rc;
3683 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3684 if (rc != 0) {
3685 pr_err("error %d\n", rc);
3705 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3706 if (rc != 0) {
3707 pr_err("error %d\n", rc);
3712 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3713 if (rc != 0) {
3714 pr_err("error %d\n", rc);
3723 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3724 if (rc != 0) {
3725 pr_err("error %d\n", rc);
3744 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3745 if (rc != 0) {
3746 pr_err("error %d\n", rc);
3751 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3752 if (rc != 0) {
3753 pr_err("error %d\n", rc);
3762 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3763 if (rc != 0) {
3764 pr_err("error %d\n", rc);
3783 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3784 if (rc != 0) {
3785 pr_err("error %d\n", rc);
3790 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3791 if (rc != 0) {
3792 pr_err("error %d\n", rc);
3801 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3802 if (rc != 0) {
3803 pr_err("error %d\n", rc);
3823 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3824 if (rc != 0) {
3825 pr_err("error %d\n", rc);
3830 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3831 if (rc != 0) {
3832 pr_err("error %d\n", rc);
3841 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3842 if (rc != 0) {
3843 pr_err("error %d\n", rc);
3853 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3854 if (rc != 0) {
3855 pr_err("error %d\n", rc);
3861 return rc;
3918 int rc;
3925 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3926 if (rc != 0) {
3927 pr_err("error %d\n", rc);
3931 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3932 if (rc != 0) {
3933 pr_err("error %d\n", rc);
3937 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3938 if (rc != 0) {
3939 pr_err("error %d\n", rc);
3943 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3944 if (rc != 0) {
3945 pr_err("error %d\n", rc);
3951 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
3952 if (rc != 0) {
3953 pr_err("error %d\n", rc);
3956 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3957 if (rc != 0) {
3958 pr_err("error %d\n", rc);
3961 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3962 if (rc != 0) {
3963 pr_err("error %d\n", rc);
3968 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3969 if (rc != 0) {
3970 pr_err("error %d\n", rc);
3976 return rc;
3981 int rc;
3990 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
3991 if (rc != 0) {
3992 pr_err("error %d\n", rc);
4000 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
4001 if (rc != 0) {
4002 pr_err("error %d\n", rc);
4007 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4008 if (rc != 0) {
4009 pr_err("error %d\n", rc);
4014 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4015 if (rc != 0) {
4016 pr_err("error %d\n", rc);
4021 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4022 if (rc != 0) {
4023 pr_err("error %d\n", rc);
4028 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4029 if (rc != 0) {
4030 pr_err("error %d\n", rc);
4041 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4042 if (rc != 0) {
4043 pr_err("error %d\n", rc);
4050 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
4051 if (rc != 0) {
4052 pr_err("error %d\n", rc);
4069 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4070 if (rc != 0) {
4071 pr_err("error %d\n", rc);
4076 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4077 if (rc != 0) {
4078 pr_err("error %d\n", rc);
4083 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4084 if (rc != 0) {
4085 pr_err("error %d\n", rc);
4090 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4091 if (rc != 0) {
4092 pr_err("error %d\n", rc);
4125 return rc;
4146 int rc;
4176 rc = scu_command(dev_addr, &scu_cmd);
4177 if (rc != 0) {
4178 pr_err("error %d\n", rc);
4194 return rc;
4210 int rc;
4216 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4217 if (rc < 0)
4218 return rc;
4224 return rc;
4238 int rc;
4243 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
4245 return rc;
4261 int rc;
4267 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
4268 if (rc != 0) {
4269 pr_err("error %d\n", rc);
4272 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
4273 if (rc != 0) {
4274 pr_err("error %d\n", rc);
4282 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4283 if (rc != 0) {
4284 pr_err("error %d\n", rc);
4289 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4290 if (rc != 0) {
4291 pr_err("error %d\n", rc);
4296 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4297 if (rc != 0) {
4298 pr_err("error %d\n", rc);
4306 return rc;
4324 int rc;
4329 rc = adc_sync_measurement(demod, &count);
4330 if (rc != 0) {
4331 pr_err("error %d\n", rc);
4339 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
4340 if (rc != 0) {
4341 pr_err("error %d\n", rc);
4346 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
4347 if (rc != 0) {
4348 pr_err("error %d\n", rc);
4352 rc = adc_sync_measurement(demod, &count);
4353 if (rc != 0) {
4354 pr_err("error %d\n", rc);
4365 return rc;
4391 int rc;
4425 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4426 if (rc != 0) {
4427 pr_err("error %d\n", rc);
4430 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4431 if (rc != 0) {
4432 pr_err("error %d\n", rc);
4435 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4436 if (rc != 0) {
4437 pr_err("error %d\n", rc);
4440 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4441 if (rc != 0) {
4442 pr_err("error %d\n", rc);
4445 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4446 if (rc != 0) {
4447 pr_err("error %d\n", rc);
4450 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4451 if (rc != 0) {
4452 pr_err("error %d\n", rc);
4455 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4456 if (rc != 0) {
4457 pr_err("error %d\n", rc);
4460 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4461 if (rc != 0) {
4462 pr_err("error %d\n", rc);
4465 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4466 if (rc != 0) {
4467 pr_err("error %d\n", rc);
4470 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4471 if (rc != 0) {
4472 pr_err("error %d\n", rc);
4475 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
4476 if (rc != 0) {
4477 pr_err("error %d\n", rc);
4480 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
4481 if (rc != 0) {
4482 pr_err("error %d\n", rc);
4485 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
4486 if (rc != 0) {
4487 pr_err("error %d\n", rc);
4508 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4509 if (rc != 0) {
4510 pr_err("error %d\n", rc);
4513 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4514 if (rc != 0) {
4515 pr_err("error %d\n", rc);
4518 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4519 if (rc != 0) {
4520 pr_err("error %d\n", rc);
4523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4524 if (rc != 0) {
4525 pr_err("error %d\n", rc);
4528 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4529 if (rc != 0) {
4530 pr_err("error %d\n", rc);
4533 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4534 if (rc != 0) {
4535 pr_err("error %d\n", rc);
4538 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4539 if (rc != 0) {
4540 pr_err("error %d\n", rc);
4543 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4544 if (rc != 0) {
4545 pr_err("error %d\n", rc);
4548 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4549 if (rc != 0) {
4550 pr_err("error %d\n", rc);
4553 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4554 if (rc != 0) {
4555 pr_err("error %d\n", rc);
4560 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4561 if (rc != 0) {
4562 pr_err("error %d\n", rc);
4566 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
4567 if (rc != 0) {
4568 pr_err("error %d\n", rc);
4572 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
4573 if (rc != 0) {
4574 pr_err("error %d\n", rc);
4584 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4585 if (rc != 0) {
4586 pr_err("error %d\n", rc);
4589 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4590 if (rc != 0) {
4591 pr_err("error %d\n", rc);
4594 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
4595 if (rc != 0) {
4596 pr_err("error %d\n", rc);
4599 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
4600 if (rc != 0) {
4601 pr_err("error %d\n", rc);
4604 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
4605 if (rc != 0) {
4606 pr_err("error %d\n", rc);
4609 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
4610 if (rc != 0) {
4611 pr_err("error %d\n", rc);
4614 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
4615 if (rc != 0) {
4616 pr_err("error %d\n", rc);
4619 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
4620 if (rc != 0) {
4621 pr_err("error %d\n", rc);
4624 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
4625 if (rc != 0) {
4626 pr_err("error %d\n", rc);
4629 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
4630 if (rc != 0) {
4631 pr_err("error %d\n", rc);
4634 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
4635 if (rc != 0) {
4636 pr_err("error %d\n", rc);
4639 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
4640 if (rc != 0) {
4641 pr_err("error %d\n", rc);
4644 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
4645 if (rc != 0) {
4646 pr_err("error %d\n", rc);
4649 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
4650 if (rc != 0) {
4651 pr_err("error %d\n", rc);
4654 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
4655 if (rc != 0) {
4656 pr_err("error %d\n", rc);
4659 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
4660 if (rc != 0) {
4661 pr_err("error %d\n", rc);
4664 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
4665 if (rc != 0) {
4666 pr_err("error %d\n", rc);
4669 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
4670 if (rc != 0) {
4671 pr_err("error %d\n", rc);
4674 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
4675 if (rc != 0) {
4676 pr_err("error %d\n", rc);
4679 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
4680 if (rc != 0) {
4681 pr_err("error %d\n", rc);
4684 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
4685 if (rc != 0) {
4686 pr_err("error %d\n", rc);
4689 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
4690 if (rc != 0) {
4691 pr_err("error %d\n", rc);
4694 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
4695 if (rc != 0) {
4696 pr_err("error %d\n", rc);
4699 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
4700 if (rc != 0) {
4701 pr_err("error %d\n", rc);
4704 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
4705 if (rc != 0) {
4706 pr_err("error %d\n", rc);
4709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
4710 if (rc != 0) {
4711 pr_err("error %d\n", rc);
4723 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
4724 if (rc != 0) {
4725 pr_err("error %d\n", rc);
4728 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
4729 if (rc != 0) {
4730 pr_err("error %d\n", rc);
4735 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4736 if (rc != 0) {
4737 pr_err("error %d\n", rc);
4742 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4743 if (rc != 0) {
4744 pr_err("error %d\n", rc);
4750 return rc;
4767 int rc;
4838 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
4839 if (rc != 0) {
4840 pr_err("error %d\n", rc);
4848 return rc;
4864 int rc;
4874 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4875 if (rc != 0) {
4876 pr_err("error %d\n", rc);
4896 return rc;
4917 int rc;
4945 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4946 if (rc != 0) {
4947 pr_err("error %d\n", rc);
4951 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4952 if (rc != 0) {
4953 pr_err("error %d\n", rc);
4958 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4959 if (rc != 0) {
4960 pr_err("error %d\n", rc);
4975 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4976 if (rc != 0) {
4977 pr_err("error %d\n", rc);
4982 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4983 if (rc != 0) {
4984 pr_err("error %d\n", rc);
4988 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4989 if (rc != 0) {
4990 pr_err("error %d\n", rc);
5005 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
5006 if (rc != 0) {
5007 pr_err("error %d\n", rc);
5010 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
5011 if (rc != 0) {
5012 pr_err("error %d\n", rc);
5018 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5019 if (rc != 0) {
5020 pr_err("error %d\n", rc);
5027 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5028 if (rc != 0) {
5029 pr_err("error %d\n", rc);
5033 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5034 if (rc != 0) {
5035 pr_err("error %d\n", rc);
5040 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5041 if (rc != 0) {
5042 pr_err("error %d\n", rc);
5050 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5051 if (rc != 0) {
5052 pr_err("error %d\n", rc);
5057 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5058 if (rc != 0) {
5059 pr_err("error %d\n", rc);
5066 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5067 if (rc != 0) {
5068 pr_err("error %d\n", rc);
5072 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5073 if (rc != 0) {
5074 pr_err("error %d\n", rc);
5079 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5080 if (rc != 0) {
5081 pr_err("error %d\n", rc);
5085 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5086 if (rc != 0) {
5087 pr_err("error %d\n", rc);
5114 return rc;
5133 int rc;
5158 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5159 if (rc != 0) {
5160 pr_err("error %d\n", rc);
5164 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5165 if (rc != 0) {
5166 pr_err("error %d\n", rc);
5171 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5172 if (rc != 0) {
5173 pr_err("error %d\n", rc);
5189 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5190 if (rc != 0) {
5191 pr_err("error %d\n", rc);
5196 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5197 if (rc != 0) {
5198 pr_err("error %d\n", rc);
5202 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5203 if (rc != 0) {
5204 pr_err("error %d\n", rc);
5219 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5220 if (rc != 0) {
5221 pr_err("error %d\n", rc);
5224 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5225 if (rc != 0) {
5226 pr_err("error %d\n", rc);
5230 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
5231 if (rc != 0) {
5232 pr_err("error %d\n", rc);
5235 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
5236 if (rc != 0) {
5237 pr_err("error %d\n", rc);
5246 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5247 if (rc != 0) {
5248 pr_err("error %d\n", rc);
5252 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5253 if (rc != 0) {
5254 pr_err("error %d\n", rc);
5259 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5260 if (rc != 0) {
5261 pr_err("error %d\n", rc);
5270 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5271 if (rc != 0) {
5272 pr_err("error %d\n", rc);
5277 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5278 if (rc != 0) {
5279 pr_err("error %d\n", rc);
5287 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5288 if (rc != 0) {
5289 pr_err("error %d\n", rc);
5293 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5294 if (rc != 0) {
5295 pr_err("error %d\n", rc);
5300 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5301 if (rc != 0) {
5302 pr_err("error %d\n", rc);
5307 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5308 if (rc != 0) {
5309 pr_err("error %d\n", rc);
5318 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5319 if (rc != 0) {
5320 pr_err("error %d\n", rc);
5343 return rc;
5357 int rc;
5362 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5363 if (rc != 0) {
5364 pr_err("error %d\n", rc);
5371 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5372 if (rc != 0) {
5373 pr_err("error %d\n", rc);
5379 return rc;
5409 int rc;
5422 rc = scu_command(dev_addr, &cmd_scu);
5423 if (rc != 0) {
5424 pr_err("error %d\n", rc);
5429 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5430 if (rc != 0) {
5431 pr_err("error %d\n", rc);
5434 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5435 if (rc != 0) {
5436 pr_err("error %d\n", rc);
5440 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
5441 if (rc != 0) {
5442 pr_err("error %d\n", rc);
5445 rc = set_iqm_af(demod, false);
5446 if (rc != 0) {
5447 pr_err("error %d\n", rc);
5451 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5452 if (rc != 0) {
5453 pr_err("error %d\n", rc);
5456 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5457 if (rc != 0) {
5458 pr_err("error %d\n", rc);
5461 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5462 if (rc != 0) {
5463 pr_err("error %d\n", rc);
5466 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5467 if (rc != 0) {
5468 pr_err("error %d\n", rc);
5471 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5472 if (rc != 0) {
5473 pr_err("error %d\n", rc);
5479 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
5480 if (rc != 0) {
5481 pr_err("error %d\n", rc);
5487 return rc;
5499 int rc;
5690 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
5691 if (rc != 0) {
5692 pr_err("error %d\n", rc);
5695 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
5696 if (rc != 0) {
5697 pr_err("error %d\n", rc);
5703 return rc;
5716 int rc;
5758 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5759 if (rc != 0) {
5760 pr_err("error %d\n", rc);
5763 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5764 if (rc != 0) {
5765 pr_err("error %d\n", rc);
5768 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5769 if (rc != 0) {
5770 pr_err("error %d\n", rc);
5773 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5774 if (rc != 0) {
5775 pr_err("error %d\n", rc);
5778 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5779 if (rc != 0) {
5780 pr_err("error %d\n", rc);
5783 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5784 if (rc != 0) {
5785 pr_err("error %d\n", rc);
5788 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5789 if (rc != 0) {
5790 pr_err("error %d\n", rc);
5801 rc = scu_command(dev_addr, &cmd_scu);
5802 if (rc != 0) {
5803 pr_err("error %d\n", rc);
5807 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
5808 if (rc != 0) {
5809 pr_err("error %d\n", rc);
5812 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
5813 if (rc != 0) {
5814 pr_err("error %d\n", rc);
5817 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
5818 if (rc != 0) {
5819 pr_err("error %d\n", rc);
5823 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
5824 if (rc != 0) {
5825 pr_err("error %d\n", rc);
5828 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
5829 if (rc != 0) {
5830 pr_err("error %d\n", rc);
5833 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
5834 if (rc != 0) {
5835 pr_err("error %d\n", rc);
5839 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
5840 if (rc != 0) {
5841 pr_err("error %d\n", rc);
5844 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
5845 if (rc != 0) {
5846 pr_err("error %d\n", rc);
5849 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
5850 if (rc != 0) {
5851 pr_err("error %d\n", rc);
5854 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
5855 if (rc != 0) {
5856 pr_err("error %d\n", rc);
5859 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
5860 if (rc != 0) {
5861 pr_err("error %d\n", rc);
5864 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
5865 if (rc != 0) {
5866 pr_err("error %d\n", rc);
5869 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
5870 if (rc != 0) {
5871 pr_err("error %d\n", rc);
5874 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
5875 if (rc != 0) {
5876 pr_err("error %d\n", rc);
5879 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
5880 if (rc != 0) {
5881 pr_err("error %d\n", rc);
5885 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5886 if (rc != 0) {
5887 pr_err("error %d\n", rc);
5890 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5891 if (rc != 0) {
5892 pr_err("error %d\n", rc);
5896 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
5897 if (rc != 0) {
5898 pr_err("error %d\n", rc);
5901 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
5902 if (rc != 0) {
5903 pr_err("error %d\n", rc);
5906 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
5907 if (rc != 0) {
5908 pr_err("error %d\n", rc);
5911 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
5912 if (rc != 0) {
5913 pr_err("error %d\n", rc);
5916 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
5917 if (rc != 0) {
5918 pr_err("error %d\n", rc);
5921 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
5922 if (rc != 0) {
5923 pr_err("error %d\n", rc);
5928 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
5929 if (rc != 0) {
5930 pr_err("error %d\n", rc);
5935 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
5936 if (rc != 0) {
5937 pr_err("error %d\n", rc);
5941 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
5942 if (rc != 0) {
5943 pr_err("error %d\n", rc);
5949 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
5950 if (rc != 0) {
5951 pr_err("error %d\n", rc);
5954 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
5955 if (rc != 0) {
5956 pr_err("error %d\n", rc);
5959 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
5960 if (rc != 0) {
5961 pr_err("error %d\n", rc);
5964 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
5965 if (rc != 0) {
5966 pr_err("error %d\n", rc);
5972 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
5973 if (rc != 0) {
5974 pr_err("error %d\n", rc);
5977 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
5978 if (rc != 0) {
5979 pr_err("error %d\n", rc);
5984 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
5985 if (rc != 0) {
5986 pr_err("error %d\n", rc);
5989 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
5990 if (rc != 0) {
5991 pr_err("error %d\n", rc);
5994 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
5995 if (rc != 0) {
5996 pr_err("error %d\n", rc);
6000 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
6001 if (rc != 0) {
6002 pr_err("error %d\n", rc);
6005 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
6006 if (rc != 0) {
6007 pr_err("error %d\n", rc);
6012 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
6013 if (rc != 0) {
6014 pr_err("error %d\n", rc);
6017 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6018 if (rc != 0) {
6019 pr_err("error %d\n", rc);
6022 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6023 if (rc != 0) {
6024 pr_err("error %d\n", rc);
6027 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6028 if (rc != 0) {
6029 pr_err("error %d\n", rc);
6033 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
6034 if (rc != 0) {
6035 pr_err("error %d\n", rc);
6040 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
6041 if (rc != 0) {
6042 pr_err("error %d\n", rc);
6048 rc = set_iqm_af(demod, true);
6049 if (rc != 0) {
6050 pr_err("error %d\n", rc);
6053 rc = adc_synchronization(demod);
6054 if (rc != 0) {
6055 pr_err("error %d\n", rc);
6059 rc = init_agc(demod);
6060 if (rc != 0) {
6061 pr_err("error %d\n", rc);
6064 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6065 if (rc != 0) {
6066 pr_err("error %d\n", rc);
6069 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6070 if (rc != 0) {
6071 pr_err("error %d\n", rc);
6080 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
6081 if (rc != 0) {
6082 pr_err("error %d\n", rc);
6086 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6087 if (rc != 0) {
6088 pr_err("error %d\n", rc);
6093 rc = set_mpegtei_handling(demod);
6094 if (rc != 0) {
6095 pr_err("error %d\n", rc);
6098 rc = bit_reverse_mpeg_output(demod);
6099 if (rc != 0) {
6100 pr_err("error %d\n", rc);
6103 rc = set_mpeg_start_width(demod);
6104 if (rc != 0) {
6105 pr_err("error %d\n", rc);
6116 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6117 if (rc != 0) {
6118 pr_err("error %d\n", rc);
6131 rc = scu_command(dev_addr, &cmd_scu);
6132 if (rc != 0) {
6133 pr_err("error %d\n", rc);
6137 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
6138 if (rc != 0) {
6139 pr_err("error %d\n", rc);
6142 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
6143 if (rc != 0) {
6144 pr_err("error %d\n", rc);
6147 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
6148 if (rc != 0) {
6149 pr_err("error %d\n", rc);
6152 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
6153 if (rc != 0) {
6154 pr_err("error %d\n", rc);
6157 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
6158 if (rc != 0) {
6159 pr_err("error %d\n", rc);
6162 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
6163 if (rc != 0) {
6164 pr_err("error %d\n", rc);
6167 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
6168 if (rc != 0) {
6169 pr_err("error %d\n", rc);
6172 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
6173 if (rc != 0) {
6174 pr_err("error %d\n", rc);
6185 rc = scu_command(dev_addr, &cmd_scu);
6186 if (rc != 0) {
6187 pr_err("error %d\n", rc);
6191 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
6192 if (rc != 0) {
6193 pr_err("error %d\n", rc);
6196 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
6197 if (rc != 0) {
6198 pr_err("error %d\n", rc);
6201 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
6202 if (rc != 0) {
6203 pr_err("error %d\n", rc);
6209 return rc;
6220 int rc;
6227 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6228 if (rc != 0) {
6229 pr_err("error %d\n", rc);
6248 return rc;
6259 int rc;
6266 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6267 if (rc != 0) {
6268 pr_err("error %d\n", rc);
6293 return rc;
6305 int rc;
6307 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6308 if (rc != 0) {
6309 pr_err("error %d\n", rc);
6325 int rc;
6328 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
6329 if (rc != 0) {
6330 pr_err("error %d\n", rc);
6338 return rc;
6367 int rc;
6378 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
6379 if (rc != 0) {
6380 pr_err("error %d\n", rc);
6383 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
6384 if (rc != 0) {
6385 pr_err("error %d\n", rc);
6395 rc = scu_command(dev_addr, &cmd_scu);
6396 if (rc != 0) {
6397 pr_err("error %d\n", rc);
6402 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
6403 if (rc != 0) {
6404 pr_err("error %d\n", rc);
6407 rc = set_iqm_af(demod, false);
6408 if (rc != 0) {
6409 pr_err("error %d\n", rc);
6413 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
6414 if (rc != 0) {
6415 pr_err("error %d\n", rc);
6418 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
6419 if (rc != 0) {
6420 pr_err("error %d\n", rc);
6423 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
6424 if (rc != 0) {
6425 pr_err("error %d\n", rc);
6428 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
6429 if (rc != 0) {
6430 pr_err("error %d\n", rc);
6433 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
6434 if (rc != 0) {
6435 pr_err("error %d\n", rc);
6443 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6444 if (rc != 0) {
6445 pr_err("error %d\n", rc);
6451 return rc;
6479 int rc;
6573 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
6574 if (rc != 0) {
6575 pr_err("error %d\n", rc);
6578 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
6579 if (rc != 0) {
6580 pr_err("error %d\n", rc);
6583 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
6584 if (rc != 0) {
6585 pr_err("error %d\n", rc);
6590 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6591 if (rc != 0) {
6592 pr_err("error %d\n", rc);
6595 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6596 if (rc != 0) {
6597 pr_err("error %d\n", rc);
6600 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6601 if (rc != 0) {
6602 pr_err("error %d\n", rc);
6647 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
6648 if (rc != 0) {
6649 pr_err("error %d\n", rc);
6652 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
6653 if (rc != 0) {
6654 pr_err("error %d\n", rc);
6663 return rc;
6677 int rc;
6695 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6696 if (rc != 0) {
6697 pr_err("error %d\n", rc);
6700 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6701 if (rc != 0) {
6702 pr_err("error %d\n", rc);
6706 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
6707 if (rc != 0) {
6708 pr_err("error %d\n", rc);
6711 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6712 if (rc != 0) {
6713 pr_err("error %d\n", rc);
6716 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
6717 if (rc != 0) {
6718 pr_err("error %d\n", rc);
6721 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
6722 if (rc != 0) {
6723 pr_err("error %d\n", rc);
6726 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
6727 if (rc != 0) {
6728 pr_err("error %d\n", rc);
6731 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
6732 if (rc != 0) {
6733 pr_err("error %d\n", rc);
6737 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6738 if (rc != 0) {
6739 pr_err("error %d\n", rc);
6742 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6743 if (rc != 0) {
6744 pr_err("error %d\n", rc);
6747 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6748 if (rc != 0) {
6749 pr_err("error %d\n", rc);
6753 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
6754 if (rc != 0) {
6755 pr_err("error %d\n", rc);
6758 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
6759 if (rc != 0) {
6760 pr_err("error %d\n", rc);
6763 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
6764 if (rc != 0) {
6765 pr_err("error %d\n", rc);
6768 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
6769 if (rc != 0) {
6770 pr_err("error %d\n", rc);
6773 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6774 if (rc != 0) {
6775 pr_err("error %d\n", rc);
6778 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6779 if (rc != 0) {
6780 pr_err("error %d\n", rc);
6783 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6784 if (rc != 0) {
6785 pr_err("error %d\n", rc);
6789 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
6790 if (rc != 0) {
6791 pr_err("error %d\n", rc);
6794 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
6795 if (rc != 0) {
6796 pr_err("error %d\n", rc);
6799 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
6800 if (rc != 0) {
6801 pr_err("error %d\n", rc);
6804 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
6805 if (rc != 0) {
6806 pr_err("error %d\n", rc);
6809 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
6810 if (rc != 0) {
6811 pr_err("error %d\n", rc);
6814 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
6815 if (rc != 0) {
6816 pr_err("error %d\n", rc);
6819 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
6820 if (rc != 0) {
6821 pr_err("error %d\n", rc);
6824 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
6825 if (rc != 0) {
6826 pr_err("error %d\n", rc);
6829 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
6830 if (rc != 0) {
6831 pr_err("error %d\n", rc);
6834 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
6835 if (rc != 0) {
6836 pr_err("error %d\n", rc);
6839 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
6840 if (rc != 0) {
6841 pr_err("error %d\n", rc);
6844 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
6845 if (rc != 0) {
6846 pr_err("error %d\n", rc);
6849 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
6850 if (rc != 0) {
6851 pr_err("error %d\n", rc);
6854 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
6855 if (rc != 0) {
6856 pr_err("error %d\n", rc);
6859 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
6860 if (rc != 0) {
6861 pr_err("error %d\n", rc);
6864 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
6865 if (rc != 0) {
6866 pr_err("error %d\n", rc);
6869 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
6870 if (rc != 0) {
6871 pr_err("error %d\n", rc);
6874 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
6875 if (rc != 0) {
6876 pr_err("error %d\n", rc);
6879 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
6880 if (rc != 0) {
6881 pr_err("error %d\n", rc);
6884 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
6885 if (rc != 0) {
6886 pr_err("error %d\n", rc);
6890 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
6891 if (rc != 0) {
6892 pr_err("error %d\n", rc);
6898 return rc;
6912 int rc;
6930 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6931 if (rc != 0) {
6932 pr_err("error %d\n", rc);
6935 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6936 if (rc != 0) {
6937 pr_err("error %d\n", rc);
6941 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
6942 if (rc != 0) {
6943 pr_err("error %d\n", rc);
6946 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6947 if (rc != 0) {
6948 pr_err("error %d\n", rc);
6951 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
6952 if (rc != 0) {
6953 pr_err("error %d\n", rc);
6956 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
6957 if (rc != 0) {
6958 pr_err("error %d\n", rc);
6961 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
6962 if (rc != 0) {
6963 pr_err("error %d\n", rc);
6966 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
6967 if (rc != 0) {
6968 pr_err("error %d\n", rc);
6972 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6973 if (rc != 0) {
6974 pr_err("error %d\n", rc);
6977 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6978 if (rc != 0) {
6979 pr_err("error %d\n", rc);
6982 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6983 if (rc != 0) {
6984 pr_err("error %d\n", rc);
6988 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
6989 if (rc != 0) {
6990 pr_err("error %d\n", rc);
6993 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
6994 if (rc != 0) {
6995 pr_err("error %d\n", rc);
6998 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
6999 if (rc != 0) {
7000 pr_err("error %d\n", rc);
7003 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
7004 if (rc != 0) {
7005 pr_err("error %d\n", rc);
7008 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
7009 if (rc != 0) {
7010 pr_err("error %d\n", rc);
7013 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7014 if (rc != 0) {
7015 pr_err("error %d\n", rc);
7018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7019 if (rc != 0) {
7020 pr_err("error %d\n", rc);
7024 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7025 if (rc != 0) {
7026 pr_err("error %d\n", rc);
7029 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7030 if (rc != 0) {
7031 pr_err("error %d\n", rc);
7034 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7035 if (rc != 0) {
7036 pr_err("error %d\n", rc);
7039 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
7040 if (rc != 0) {
7041 pr_err("error %d\n", rc);
7044 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7045 if (rc != 0) {
7046 pr_err("error %d\n", rc);
7049 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7050 if (rc != 0) {
7051 pr_err("error %d\n", rc);
7054 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
7055 if (rc != 0) {
7056 pr_err("error %d\n", rc);
7059 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
7060 if (rc != 0) {
7061 pr_err("error %d\n", rc);
7064 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7065 if (rc != 0) {
7066 pr_err("error %d\n", rc);
7069 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7070 if (rc != 0) {
7071 pr_err("error %d\n", rc);
7074 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7075 if (rc != 0) {
7076 pr_err("error %d\n", rc);
7079 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7080 if (rc != 0) {
7081 pr_err("error %d\n", rc);
7084 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7085 if (rc != 0) {
7086 pr_err("error %d\n", rc);
7089 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7090 if (rc != 0) {
7091 pr_err("error %d\n", rc);
7094 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7095 if (rc != 0) {
7096 pr_err("error %d\n", rc);
7099 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7100 if (rc != 0) {
7101 pr_err("error %d\n", rc);
7104 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
7105 if (rc != 0) {
7106 pr_err("error %d\n", rc);
7109 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7110 if (rc != 0) {
7111 pr_err("error %d\n", rc);
7114 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7115 if (rc != 0) {
7116 pr_err("error %d\n", rc);
7119 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
7120 if (rc != 0) {
7121 pr_err("error %d\n", rc);
7125 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
7126 if (rc != 0) {
7127 pr_err("error %d\n", rc);
7133 return rc;
7147 int rc;
7166 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7167 if (rc != 0) {
7168 pr_err("error %d\n", rc);
7171 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7172 if (rc != 0) {
7173 pr_err("error %d\n", rc);
7177 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
7178 if (rc != 0) {
7179 pr_err("error %d\n", rc);
7182 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7183 if (rc != 0) {
7184 pr_err("error %d\n", rc);
7187 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7188 if (rc != 0) {
7189 pr_err("error %d\n", rc);
7192 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
7193 if (rc != 0) {
7194 pr_err("error %d\n", rc);
7197 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7198 if (rc != 0) {
7199 pr_err("error %d\n", rc);
7202 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
7203 if (rc != 0) {
7204 pr_err("error %d\n", rc);
7208 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7209 if (rc != 0) {
7210 pr_err("error %d\n", rc);
7213 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7214 if (rc != 0) {
7215 pr_err("error %d\n", rc);
7218 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7219 if (rc != 0) {
7220 pr_err("error %d\n", rc);
7224 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
7225 if (rc != 0) {
7226 pr_err("error %d\n", rc);
7229 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
7230 if (rc != 0) {
7231 pr_err("error %d\n", rc);
7234 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
7235 if (rc != 0) {
7236 pr_err("error %d\n", rc);
7239 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
7240 if (rc != 0) {
7241 pr_err("error %d\n", rc);
7244 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7245 if (rc != 0) {
7246 pr_err("error %d\n", rc);
7249 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7250 if (rc != 0) {
7251 pr_err("error %d\n", rc);
7254 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7255 if (rc != 0) {
7256 pr_err("error %d\n", rc);
7260 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7261 if (rc != 0) {
7262 pr_err("error %d\n", rc);
7265 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7266 if (rc != 0) {
7267 pr_err("error %d\n", rc);
7270 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7271 if (rc != 0) {
7272 pr_err("error %d\n", rc);
7275 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
7276 if (rc != 0) {
7277 pr_err("error %d\n", rc);
7280 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7281 if (rc != 0) {
7282 pr_err("error %d\n", rc);
7285 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7286 if (rc != 0) {
7287 pr_err("error %d\n", rc);
7290 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
7291 if (rc != 0) {
7292 pr_err("error %d\n", rc);
7295 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7296 if (rc != 0) {
7297 pr_err("error %d\n", rc);
7300 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7301 if (rc != 0) {
7302 pr_err("error %d\n", rc);
7305 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7306 if (rc != 0) {
7307 pr_err("error %d\n", rc);
7310 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7311 if (rc != 0) {
7312 pr_err("error %d\n", rc);
7315 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7316 if (rc != 0) {
7317 pr_err("error %d\n", rc);
7320 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7321 if (rc != 0) {
7322 pr_err("error %d\n", rc);
7325 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7326 if (rc != 0) {
7327 pr_err("error %d\n", rc);
7330 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7331 if (rc != 0) {
7332 pr_err("error %d\n", rc);
7335 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7336 if (rc != 0) {
7337 pr_err("error %d\n", rc);
7340 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
7341 if (rc != 0) {
7342 pr_err("error %d\n", rc);
7345 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7346 if (rc != 0) {
7347 pr_err("error %d\n", rc);
7350 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7351 if (rc != 0) {
7352 pr_err("error %d\n", rc);
7355 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
7356 if (rc != 0) {
7357 pr_err("error %d\n", rc);
7361 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
7362 if (rc != 0) {
7363 pr_err("error %d\n", rc);
7369 return rc;
7383 int rc;
7401 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7402 if (rc != 0) {
7403 pr_err("error %d\n", rc);
7406 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7407 if (rc != 0) {
7408 pr_err("error %d\n", rc);
7412 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7413 if (rc != 0) {
7414 pr_err("error %d\n", rc);
7417 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7418 if (rc != 0) {
7419 pr_err("error %d\n", rc);
7422 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7423 if (rc != 0) {
7424 pr_err("error %d\n", rc);
7427 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
7428 if (rc != 0) {
7429 pr_err("error %d\n", rc);
7432 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7433 if (rc != 0) {
7434 pr_err("error %d\n", rc);
7437 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
7438 if (rc != 0) {
7439 pr_err("error %d\n", rc);
7443 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7444 if (rc != 0) {
7445 pr_err("error %d\n", rc);
7448 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7449 if (rc != 0) {
7450 pr_err("error %d\n", rc);
7453 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7454 if (rc != 0) {
7455 pr_err("error %d\n", rc);
7459 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7460 if (rc != 0) {
7461 pr_err("error %d\n", rc);
7464 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
7465 if (rc != 0) {
7466 pr_err("error %d\n", rc);
7469 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
7470 if (rc != 0) {
7471 pr_err("error %d\n", rc);
7474 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
7475 if (rc != 0) {
7476 pr_err("error %d\n", rc);
7479 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7480 if (rc != 0) {
7481 pr_err("error %d\n", rc);
7484 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
7485 if (rc != 0) {
7486 pr_err("error %d\n", rc);
7489 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7490 if (rc != 0) {
7491 pr_err("error %d\n", rc);
7495 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7496 if (rc != 0) {
7497 pr_err("error %d\n", rc);
7500 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7501 if (rc != 0) {
7502 pr_err("error %d\n", rc);
7505 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7506 if (rc != 0) {
7507 pr_err("error %d\n", rc);
7510 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
7511 if (rc != 0) {
7512 pr_err("error %d\n", rc);
7515 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7516 if (rc != 0) {
7517 pr_err("error %d\n", rc);
7520 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7521 if (rc != 0) {
7522 pr_err("error %d\n", rc);
7525 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
7526 if (rc != 0) {
7527 pr_err("error %d\n", rc);
7530 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7531 if (rc != 0) {
7532 pr_err("error %d\n", rc);
7535 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7536 if (rc != 0) {
7537 pr_err("error %d\n", rc);
7540 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7541 if (rc != 0) {
7542 pr_err("error %d\n", rc);
7545 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7546 if (rc != 0) {
7547 pr_err("error %d\n", rc);
7550 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7551 if (rc != 0) {
7552 pr_err("error %d\n", rc);
7555 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7556 if (rc != 0) {
7557 pr_err("error %d\n", rc);
7560 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7561 if (rc != 0) {
7562 pr_err("error %d\n", rc);
7565 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7566 if (rc != 0) {
7567 pr_err("error %d\n", rc);
7570 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7571 if (rc != 0) {
7572 pr_err("error %d\n", rc);
7575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
7576 if (rc != 0) {
7577 pr_err("error %d\n", rc);
7580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7581 if (rc != 0) {
7582 pr_err("error %d\n", rc);
7585 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7586 if (rc != 0) {
7587 pr_err("error %d\n", rc);
7590 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7591 if (rc != 0) {
7592 pr_err("error %d\n", rc);
7596 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
7597 if (rc != 0) {
7598 pr_err("error %d\n", rc);
7604 return rc;
7618 int rc;
7636 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7637 if (rc != 0) {
7638 pr_err("error %d\n", rc);
7641 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7642 if (rc != 0) {
7643 pr_err("error %d\n", rc);
7647 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7648 if (rc != 0) {
7649 pr_err("error %d\n", rc);
7652 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7653 if (rc != 0) {
7654 pr_err("error %d\n", rc);
7657 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7658 if (rc != 0) {
7659 pr_err("error %d\n", rc);
7662 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
7663 if (rc != 0) {
7664 pr_err("error %d\n", rc);
7667 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7668 if (rc != 0) {
7669 pr_err("error %d\n", rc);
7672 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
7673 if (rc != 0) {
7674 pr_err("error %d\n", rc);
7678 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7679 if (rc != 0) {
7680 pr_err("error %d\n", rc);
7683 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
7684 if (rc != 0) {
7685 pr_err("error %d\n", rc);
7688 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7689 if (rc != 0) {
7690 pr_err("error %d\n", rc);
7694 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7695 if (rc != 0) {
7696 pr_err("error %d\n", rc);
7699 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
7700 if (rc != 0) {
7701 pr_err("error %d\n", rc);
7704 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
7705 if (rc != 0) {
7706 pr_err("error %d\n", rc);
7709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
7710 if (rc != 0) {
7711 pr_err("error %d\n", rc);
7714 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
7715 if (rc != 0) {
7716 pr_err("error %d\n", rc);
7719 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
7720 if (rc != 0) {
7721 pr_err("error %d\n", rc);
7724 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7725 if (rc != 0) {
7726 pr_err("error %d\n", rc);
7730 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7731 if (rc != 0) {
7732 pr_err("error %d\n", rc);
7735 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7736 if (rc != 0) {
7737 pr_err("error %d\n", rc);
7740 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7741 if (rc != 0) {
7742 pr_err("error %d\n", rc);
7745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
7746 if (rc != 0) {
7747 pr_err("error %d\n", rc);
7750 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7751 if (rc != 0) {
7752 pr_err("error %d\n", rc);
7755 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7756 if (rc != 0) {
7757 pr_err("error %d\n", rc);
7760 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
7761 if (rc != 0) {
7762 pr_err("error %d\n", rc);
7765 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7766 if (rc != 0) {
7767 pr_err("error %d\n", rc);
7770 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7771 if (rc != 0) {
7772 pr_err("error %d\n", rc);
7775 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7776 if (rc != 0) {
7777 pr_err("error %d\n", rc);
7780 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7781 if (rc != 0) {
7782 pr_err("error %d\n", rc);
7785 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7786 if (rc != 0) {
7787 pr_err("error %d\n", rc);
7790 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7791 if (rc != 0) {
7792 pr_err("error %d\n", rc);
7795 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7796 if (rc != 0) {
7797 pr_err("error %d\n", rc);
7800 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7801 if (rc != 0) {
7802 pr_err("error %d\n", rc);
7805 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7806 if (rc != 0) {
7807 pr_err("error %d\n", rc);
7810 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
7811 if (rc != 0) {
7812 pr_err("error %d\n", rc);
7815 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7816 if (rc != 0) {
7817 pr_err("error %d\n", rc);
7820 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7821 if (rc != 0) {
7822 pr_err("error %d\n", rc);
7825 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7826 if (rc != 0) {
7827 pr_err("error %d\n", rc);
7831 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
7832 if (rc != 0) {
7833 pr_err("error %d\n", rc);
7839 return rc;
7861 int rc;
8065 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
8066 if (rc != 0) {
8067 pr_err("error %d\n", rc);
8070 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
8071 if (rc != 0) {
8072 pr_err("error %d\n", rc);
8075 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
8076 if (rc != 0) {
8077 pr_err("error %d\n", rc);
8080 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
8081 if (rc != 0) {
8082 pr_err("error %d\n", rc);
8085 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
8086 if (rc != 0) {
8087 pr_err("error %d\n", rc);
8090 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
8091 if (rc != 0) {
8092 pr_err("error %d\n", rc);
8095 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
8096 if (rc != 0) {
8097 pr_err("error %d\n", rc);
8107 rc = scu_command(dev_addr, &cmd_scu);
8108 if (rc != 0) {
8109 pr_err("error %d\n", rc);
8126 rc = scu_command(dev_addr, &cmd_scu);
8127 if (rc != 0) {
8128 pr_err("error %d\n", rc);
8138 rc = scu_command(dev_addr, &cmd_scu);
8139 if (rc != 0) {
8140 pr_err("error %d\n", rc);
8144 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
8145 if (rc != 0) {
8146 pr_err("error %d\n", rc);
8150 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8151 if (rc != 0) {
8152 pr_err("error %d\n", rc);
8161 rc = set_frequency(demod, channel, tuner_freq_offset);
8162 if (rc != 0) {
8163 pr_err("error %d\n", rc);
8170 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
8171 if (rc != 0) {
8172 pr_err("error %d\n", rc);
8175 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
8176 if (rc != 0) {
8177 pr_err("error %d\n", rc);
8184 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
8185 if (rc != 0) {
8186 pr_err("error %d\n", rc);
8190 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
8191 if (rc != 0) {
8192 pr_err("error %d\n", rc);
8195 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
8196 if (rc != 0) {
8197 pr_err("error %d\n", rc);
8200 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
8201 if (rc != 0) {
8202 pr_err("error %d\n", rc);
8206 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
8207 if (rc != 0) {
8208 pr_err("error %d\n", rc);
8212 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
8213 if (rc != 0) {
8214 pr_err("error %d\n", rc);
8217 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
8218 if (rc != 0) {
8219 pr_err("error %d\n", rc);
8222 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
8223 if (rc != 0) {
8224 pr_err("error %d\n", rc);
8227 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
8228 if (rc != 0) {
8229 pr_err("error %d\n", rc);
8232 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
8233 if (rc != 0) {
8234 pr_err("error %d\n", rc);
8237 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
8238 if (rc != 0) {
8239 pr_err("error %d\n", rc);
8242 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
8243 if (rc != 0) {
8244 pr_err("error %d\n", rc);
8248 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
8249 if (rc != 0) {
8250 pr_err("error %d\n", rc);
8253 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
8254 if (rc != 0) {
8255 pr_err("error %d\n", rc);
8259 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
8260 if (rc != 0) {
8261 pr_err("error %d\n", rc);
8265 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
8266 if (rc != 0) {
8267 pr_err("error %d\n", rc);
8270 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
8271 if (rc != 0) {
8272 pr_err("error %d\n", rc);
8275 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8276 if (rc != 0) {
8277 pr_err("error %d\n", rc);
8285 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8286 if (rc != 0) {
8287 pr_err("error %d\n", rc);
8290 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
8291 if (rc != 0) {
8292 pr_err("error %d\n", rc);
8295 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8296 if (rc != 0) {
8297 pr_err("error %d\n", rc);
8303 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8304 if (rc != 0) {
8305 pr_err("error %d\n", rc);
8308 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
8309 if (rc != 0) {
8310 pr_err("error %d\n", rc);
8313 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
8314 if (rc != 0) {
8315 pr_err("error %d\n", rc);
8324 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
8325 if (rc != 0) {
8326 pr_err("error %d\n", rc);
8329 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
8330 if (rc != 0) {
8331 pr_err("error %d\n", rc);
8334 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
8335 if (rc != 0) {
8336 pr_err("error %d\n", rc);
8339 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
8340 if (rc != 0) {
8341 pr_err("error %d\n", rc);
8344 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
8345 if (rc != 0) {
8346 pr_err("error %d\n", rc);
8349 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
8350 if (rc != 0) {
8351 pr_err("error %d\n", rc);
8354 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
8355 if (rc != 0) {
8356 pr_err("error %d\n", rc);
8359 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
8360 if (rc != 0) {
8361 pr_err("error %d\n", rc);
8364 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
8365 if (rc != 0) {
8366 pr_err("error %d\n", rc);
8369 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
8370 if (rc != 0) {
8371 pr_err("error %d\n", rc);
8374 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
8375 if (rc != 0) {
8376 pr_err("error %d\n", rc);
8379 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
8380 if (rc != 0) {
8381 pr_err("error %d\n", rc);
8384 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
8385 if (rc != 0) {
8386 pr_err("error %d\n", rc);
8389 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
8390 if (rc != 0) {
8391 pr_err("error %d\n", rc);
8394 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
8395 if (rc != 0) {
8396 pr_err("error %d\n", rc);
8399 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
8400 if (rc != 0) {
8401 pr_err("error %d\n", rc);
8404 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
8405 if (rc != 0) {
8406 pr_err("error %d\n", rc);
8409 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
8410 if (rc != 0) {
8411 pr_err("error %d\n", rc);
8414 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
8415 if (rc != 0) {
8416 pr_err("error %d\n", rc);
8419 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
8420 if (rc != 0) {
8421 pr_err("error %d\n", rc);
8425 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
8426 if (rc != 0) {
8427 pr_err("error %d\n", rc);
8430 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
8431 if (rc != 0) {
8432 pr_err("error %d\n", rc);
8435 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
8436 if (rc != 0) {
8437 pr_err("error %d\n", rc);
8440 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
8441 if (rc != 0) {
8442 pr_err("error %d\n", rc);
8445 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
8446 if (rc != 0) {
8447 pr_err("error %d\n", rc);
8454 rc = set_iqm_af(demod, true);
8455 if (rc != 0) {
8456 pr_err("error %d\n", rc);
8459 rc = adc_synchronization(demod);
8460 if (rc != 0) {
8461 pr_err("error %d\n", rc);
8465 rc = init_agc(demod);
8466 if (rc != 0) {
8467 pr_err("error %d\n", rc);
8470 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8471 if (rc != 0) {
8472 pr_err("error %d\n", rc);
8475 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8476 if (rc != 0) {
8477 pr_err("error %d\n", rc);
8486 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
8487 if (rc != 0) {
8488 pr_err("error %d\n", rc);
8492 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8493 if (rc != 0) {
8494 pr_err("error %d\n", rc);
8501 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8502 if (rc != 0) {
8503 pr_err("error %d\n", rc);
8506 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8507 if (rc != 0) {
8508 pr_err("error %d\n", rc);
8514 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8515 if (rc != 0) {
8516 pr_err("error %d\n", rc);
8519 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8520 if (rc != 0) {
8521 pr_err("error %d\n", rc);
8526 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8527 if (rc != 0) {
8528 pr_err("error %d\n", rc);
8531 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8532 if (rc != 0) {
8533 pr_err("error %d\n", rc);
8541 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8542 if (rc != 0) {
8543 pr_err("error %d\n", rc);
8546 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8547 if (rc != 0) {
8548 pr_err("error %d\n", rc);
8556 rc = set_qam16(demod);
8557 if (rc != 0) {
8558 pr_err("error %d\n", rc);
8563 rc = set_qam32(demod);
8564 if (rc != 0) {
8565 pr_err("error %d\n", rc);
8570 rc = set_qam64(demod);
8571 if (rc != 0) {
8572 pr_err("error %d\n", rc);
8577 rc = set_qam128(demod);
8578 if (rc != 0) {
8579 pr_err("error %d\n", rc);
8584 rc = set_qam256(demod);
8585 if (rc != 0) {
8586 pr_err("error %d\n", rc);
8596 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
8597 if (rc != 0) {
8598 pr_err("error %d\n", rc);
8603 rc = set_mpegtei_handling(demod);
8604 if (rc != 0) {
8605 pr_err("error %d\n", rc);
8608 rc = bit_reverse_mpeg_output(demod);
8609 if (rc != 0) {
8610 pr_err("error %d\n", rc);
8613 rc = set_mpeg_start_width(demod);
8614 if (rc != 0) {
8615 pr_err("error %d\n", rc);
8626 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
8627 if (rc != 0) {
8628 pr_err("error %d\n", rc);
8643 rc = scu_command(dev_addr, &cmd_scu);
8644 if (rc != 0) {
8645 pr_err("error %d\n", rc);
8650 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
8651 if (rc != 0) {
8652 pr_err("error %d\n", rc);
8655 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
8656 if (rc != 0) {
8657 pr_err("error %d\n", rc);
8660 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
8661 if (rc != 0) {
8662 pr_err("error %d\n", rc);
8668 return rc;
8678 int rc;
8689 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
8690 if (rc != 0) {
8691 pr_err("error %d\n", rc);
8694 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
8695 if (rc != 0) {
8696 pr_err("error %d\n", rc);
8701 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
8702 if (rc != 0) {
8703 pr_err("error %d\n", rc);
8706 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
8707 if (rc != 0) {
8708 pr_err("error %d\n", rc);
8712 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
8713 if (rc != 0) {
8714 pr_err("error %d\n", rc);
8717 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
8718 if (rc != 0) {
8719 pr_err("error %d\n", rc);
8727 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8728 if (rc != 0) {
8729 pr_err("error %d\n", rc);
8733 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8734 if (rc != 0) {
8735 pr_err("error %d\n", rc);
8738 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8739 if (rc != 0) {
8740 pr_err("error %d\n", rc);
8745 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
8746 if (rc != 0) {
8747 pr_err("error %d\n", rc);
8750 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
8751 if (rc != 0) {
8752 pr_err("error %d\n", rc);
8755 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
8756 if (rc != 0) {
8757 pr_err("error %d\n", rc);
8762 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
8763 if (rc != 0) {
8764 pr_err("error %d\n", rc);
8771 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8772 if (rc != 0) {
8773 pr_err("error %d\n", rc);
8778 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8779 if (rc != 0) {
8780 pr_err("error %d\n", rc);
8783 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8784 if (rc != 0) {
8785 pr_err("error %d\n", rc);
8790 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8791 if (rc != 0) {
8792 pr_err("error %d\n", rc);
8795 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8796 if (rc != 0) {
8797 pr_err("error %d\n", rc);
8803 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8804 if (rc != 0) {
8805 pr_err("error %d\n", rc);
8808 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8809 if (rc != 0) {
8810 pr_err("error %d\n", rc);
8816 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8817 if (rc != 0) {
8818 pr_err("error %d\n", rc);
8821 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8822 if (rc != 0) {
8823 pr_err("error %d\n", rc);
8827 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
8828 if (rc != 0) {
8829 pr_err("error %d\n", rc);
8835 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
8836 if (rc != 0) {
8837 pr_err("error %d\n", rc);
8841 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
8842 if (rc != 0) {
8843 pr_err("error %d\n", rc);
8849 return rc;
8875 int rc;
8887 rc = ctrl_lock_status(demod, lock_status);
8888 if (rc != 0) {
8889 pr_err("error %d\n", rc);
8896 rc = ctrl_get_qam_sig_quality(demod);
8897 if (rc != 0) {
8898 pr_err("error %d\n", rc);
8913 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8914 if (rc != 0) {
8915 pr_err("error %d\n", rc);
8918 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8919 if (rc != 0) {
8920 pr_err("error %d\n", rc);
8931 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8932 if (rc != 0) {
8933 pr_err("error %d\n", rc);
8936 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8937 if (rc != 0) {
8938 pr_err("error %d\n", rc);
8943 rc = qam_flip_spec(demod, channel);
8944 if (rc != 0) {
8945 pr_err("error %d\n", rc);
8965 rc = ctrl_get_qam_sig_quality(demod);
8966 if (rc != 0) {
8967 pr_err("error %d\n", rc);
8971 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8972 if (rc != 0) {
8973 pr_err("error %d\n", rc);
8976 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8977 if (rc != 0) {
8978 pr_err("error %d\n", rc);
9002 return rc;
9023 int rc;
9034 rc = ctrl_lock_status(demod, lock_status);
9035 if (rc != 0) {
9036 pr_err("error %d\n", rc);
9042 rc = ctrl_get_qam_sig_quality(demod);
9043 if (rc != 0) {
9044 pr_err("error %d\n", rc);
9060 rc = qam_flip_spec(demod, channel);
9061 if (rc != 0) {
9062 pr_err("error %d\n", rc);
9086 return rc;
9101 int rc;
9125 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
9126 if (rc != 0) {
9127 pr_err("error %d\n", rc);
9132 rc = qam64auto(demod, channel, tuner_freq_offset,
9135 rc = qam256auto(demod, channel, tuner_freq_offset,
9137 if (rc != 0) {
9138 pr_err("error %d\n", rc);
9155 rc = set_qam(demod, channel, tuner_freq_offset,
9157 if (rc != 0) {
9158 pr_err("error %d\n", rc);
9161 rc = qam256auto(demod, channel, tuner_freq_offset,
9163 if (rc != 0) {
9164 pr_err("error %d\n", rc);
9181 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9184 if (rc != 0) {
9185 pr_err("error %d\n", rc);
9188 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9191 if (rc != 0) {
9192 pr_err("error %d\n", rc);
9195 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9198 if (rc != 0) {
9199 pr_err("error %d\n", rc);
9203 rc = set_qam(demod, channel, tuner_freq_offset,
9205 if (rc != 0) {
9206 pr_err("error %d\n", rc);
9209 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9212 if (rc != 0) {
9213 pr_err("error %d\n", rc);
9217 rc = qam64auto(demod, channel, tuner_freq_offset,
9219 if (rc != 0) {
9220 pr_err("error %d\n", rc);
9236 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9239 if (rc != 0) {
9240 pr_err("error %d\n", rc);
9243 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9246 if (rc != 0) {
9247 pr_err("error %d\n", rc);
9250 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9253 if (rc != 0) {
9254 pr_err("error %d\n", rc);
9258 rc = set_qam(demod, channel, tuner_freq_offset,
9260 if (rc != 0) {
9261 pr_err("error %d\n", rc);
9264 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9267 if (rc != 0) {
9268 pr_err("error %d\n", rc);
9271 rc = qam64auto(demod, channel, tuner_freq_offset,
9273 if (rc != 0) {
9274 pr_err("error %d\n", rc);
9291 return rc;
9308 int rc;
9320 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
9321 if (rc != 0) {
9322 pr_err("error %d\n", rc);
9326 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
9327 if (rc != 0) {
9328 pr_err("error %d\n", rc);
9332 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
9333 if (rc != 0) {
9334 pr_err("error %d\n", rc);
9338 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
9339 if (rc != 0) {
9340 pr_err("error %d\n", rc);
9344 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
9345 if (rc != 0) {
9346 pr_err("error %d\n", rc);
9362 return rc;
9385 int rc;
9393 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
9394 if (rc != 0) {
9395 pr_err("error %d\n", rc);
9399 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
9400 if (rc != 0) {
9401 pr_err("error %d\n", rc);
9444 return rc;
9468 int rc;
9498 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
9499 if (rc != 0) {
9500 pr_err("error %d\n", rc);
9504 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
9505 if (rc != 0) {
9506 pr_err("error %d\n", rc);
9510 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
9511 if (rc != 0) {
9512 pr_err("error %d\n", rc);
9542 rc = -EIO;
9564 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
9565 if (rc != 0) {
9566 pr_err("error %d\n", rc);
9647 rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9648 if (rc != 0) {
9649 pr_err("error %d\n", rc);
9663 return rc;
9755 int rc;
9767 rc = scu_command(dev_addr, &cmd_scu);
9768 if (rc != 0) {
9769 pr_err("error %d\n", rc);
9773 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
9774 if (rc != 0) {
9775 pr_err("error %d\n", rc);
9779 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
9780 if (rc != 0) {
9781 pr_err("error %d\n", rc);
9785 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
9786 if (rc != 0) {
9787 pr_err("error %d\n", rc);
9790 rc = set_iqm_af(demod, false);
9791 if (rc != 0) {
9792 pr_err("error %d\n", rc);
9796 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
9797 if (rc != 0) {
9798 pr_err("error %d\n", rc);
9801 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
9802 if (rc != 0) {
9803 pr_err("error %d\n", rc);
9806 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
9807 if (rc != 0) {
9808 pr_err("error %d\n", rc);
9811 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
9812 if (rc != 0) {
9813 pr_err("error %d\n", rc);
9816 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
9817 if (rc != 0) {
9818 pr_err("error %d\n", rc);
9822 rc = power_down_aud(demod);
9823 if (rc != 0) {
9824 pr_err("error %d\n", rc);
9830 return rc;
9845 int rc;
9850 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
9851 if (rc != 0) {
9852 pr_err("error %d\n", rc);
9860 return rc;
9873 int rc;
9877 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9878 if (rc != 0) {
9879 pr_err("error %d\n", rc);
9886 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
9887 if (rc != 0) {
9888 pr_err("error %d\n", rc);
9894 return rc;
9923 int rc;
9960 rc = scu_command(dev_addr, &scu_cmd);
9961 if (rc != 0) {
9962 pr_err("error %d\n", rc);
9965 rc = set_orx_nsu_aox(demod, false);
9966 if (rc != 0) {
9967 pr_err("error %d\n", rc);
9970 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9971 if (rc != 0) {
9972 pr_err("error %d\n", rc);
10002 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
10003 if (rc != 0) {
10004 pr_err("error %d\n", rc);
10012 rc = scu_command(dev_addr, &scu_cmd);
10013 if (rc != 0) {
10014 pr_err("error %d\n", rc);
10025 rc = scu_command(dev_addr, &scu_cmd);
10026 if (rc != 0) {
10027 pr_err("error %d\n", rc);
10101 rc = scu_command(dev_addr, &scu_cmd);
10102 if (rc != 0) {
10103 pr_err("error %d\n", rc);
10107 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
10108 if (rc != 0) {
10109 pr_err("error %d\n", rc);
10112 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
10113 if (rc != 0) {
10114 pr_err("error %d\n", rc);
10117 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
10118 if (rc != 0) {
10119 pr_err("error %d\n", rc);
10122 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
10123 if (rc != 0) {
10124 pr_err("error %d\n", rc);
10128 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
10129 if (rc != 0) {
10130 pr_err("error %d\n", rc);
10133 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
10134 if (rc != 0) {
10135 pr_err("error %d\n", rc);
10138 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
10139 if (rc != 0) {
10140 pr_err("error %d\n", rc);
10145 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
10146 if (rc != 0) {
10147 pr_err("error %d\n", rc);
10152 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10153 if (rc != 0) {
10154 pr_err("error %d\n", rc);
10159 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
10160 if (rc != 0) {
10161 pr_err("error %d\n", rc);
10164 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
10165 if (rc != 0) {
10166 pr_err("error %d\n", rc);
10171 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
10172 if (rc != 0) {
10173 pr_err("error %d\n", rc);
10176 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
10177 if (rc != 0) {
10178 pr_err("error %d\n", rc);
10181 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
10182 if (rc != 0) {
10183 pr_err("error %d\n", rc);
10186 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
10187 if (rc != 0) {
10188 pr_err("error %d\n", rc);
10193 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
10194 if (rc != 0) {
10195 pr_err("error %d\n", rc);
10198 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10199 if (rc != 0) {
10200 pr_err("error %d\n", rc);
10203 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
10204 if (rc != 0) {
10205 pr_err("error %d\n", rc);
10208 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10209 if (rc != 0) {
10210 pr_err("error %d\n", rc);
10213 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
10214 if (rc != 0) {
10215 pr_err("error %d\n", rc);
10220 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
10221 if (rc != 0) {
10222 pr_err("error %d\n", rc);
10225 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10226 if (rc != 0) {
10227 pr_err("error %d\n", rc);
10230 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
10231 if (rc != 0) {
10232 pr_err("error %d\n", rc);
10235 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10236 if (rc != 0) {
10237 pr_err("error %d\n", rc);
10240 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
10241 if (rc != 0) {
10242 pr_err("error %d\n", rc);
10247 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
10248 if (rc != 0) {
10249 pr_err("error %d\n", rc);
10252 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10253 if (rc != 0) {
10254 pr_err("error %d\n", rc);
10257 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
10258 if (rc != 0) {
10259 pr_err("error %d\n", rc);
10262 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10263 if (rc != 0) {
10264 pr_err("error %d\n", rc);
10267 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
10268 if (rc != 0) {
10269 pr_err("error %d\n", rc);
10274 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
10275 if (rc != 0) {
10276 pr_err("error %d\n", rc);
10279 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10280 if (rc != 0) {
10281 pr_err("error %d\n", rc);
10284 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
10285 if (rc != 0) {
10286 pr_err("error %d\n", rc);
10289 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10290 if (rc != 0) {
10291 pr_err("error %d\n", rc);
10294 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
10295 if (rc != 0) {
10296 pr_err("error %d\n", rc);
10301 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
10302 if (rc != 0) {
10303 pr_err("error %d\n", rc);
10306 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10307 if (rc != 0) {
10308 pr_err("error %d\n", rc);
10311 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
10312 if (rc != 0) {
10313 pr_err("error %d\n", rc);
10316 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10317 if (rc != 0) {
10318 pr_err("error %d\n", rc);
10321 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
10322 if (rc != 0) {
10323 pr_err("error %d\n", rc);
10328 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
10329 if (rc != 0) {
10330 pr_err("error %d\n", rc);
10333 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10334 if (rc != 0) {
10335 pr_err("error %d\n", rc);
10338 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
10339 if (rc != 0) {
10340 pr_err("error %d\n", rc);
10343 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10344 if (rc != 0) {
10345 pr_err("error %d\n", rc);
10348 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
10349 if (rc != 0) {
10350 pr_err("error %d\n", rc);
10355 rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
10356 if (rc != 0) {
10357 pr_err("error %d\n", rc);
10360 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
10361 if (rc != 0) {
10362 pr_err("error %d\n", rc);
10368 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
10369 if (rc != 0) {
10370 pr_err("error %d\n", rc);
10373 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
10374 if (rc != 0) {
10375 pr_err("error %d\n", rc);
10379 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
10380 if (rc != 0) {
10381 pr_err("error %d\n", rc);
10384 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
10385 if (rc != 0) {
10386 pr_err("error %d\n", rc);
10397 rc = scu_command(dev_addr, &scu_cmd);
10398 if (rc != 0) {
10399 pr_err("error %d\n", rc);
10403 rc = set_orx_nsu_aox(demod, true);
10404 if (rc != 0) {
10405 pr_err("error %d\n", rc);
10408 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10409 if (rc != 0) {
10410 pr_err("error %d\n", rc);
10418 return rc;
10446 int rc;
10509 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
10510 if (rc != 0) {
10511 pr_err("error %d\n", rc);
10604 rc = ctrl_uio_write(demod, &uio1);
10605 if (rc != 0) {
10606 pr_err("error %d\n", rc);
10611 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
10612 if (rc != 0) {
10613 pr_err("error %d\n", rc);
10626 rc = set_vsb(demod);
10627 if (rc != 0) {
10628 pr_err("error %d\n", rc);
10631 rc = set_frequency(demod, channel, tuner_freq_offset);
10632 if (rc != 0) {
10633 pr_err("error %d\n", rc);
10641 rc = set_qam_channel(demod, channel, tuner_freq_offset);
10642 if (rc != 0) {
10643 pr_err("error %d\n", rc);
10658 return rc;
10685 int rc;
10689 rc = get_sig_strength(demod, &strength);
10690 if (rc < 0) {
10691 pr_err("error getting signal strength %d\n", rc);
10701 rc = get_acc_pkt_err(demod, &pkt);
10702 if (rc != 0) {
10703 pr_err("error %d\n", rc);
10716 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
10717 if (rc != 0) {
10718 pr_err("error %d getting UCB\n", rc);
10728 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
10729 if (rc != 0) {
10730 pr_err("error %d getting pre-ber\n", rc);
10739 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
10740 if (rc != 0) {
10741 pr_err("error %d getting post-ber\n", rc);
10749 rc = get_vsbmer(dev_addr, &mer);
10750 if (rc != 0) {
10751 pr_err("error %d getting MER\n", rc);
10763 rc = ctrl_get_qam_sig_quality(demod);
10764 if (rc != 0) {
10765 pr_err("error %d\n", rc);
10776 return rc;
10801 int rc;
10840 rc = scu_command(dev_addr, &cmd_scu);
10841 if (rc != 0) {
10842 pr_err("error %d\n", rc);
10864 return rc;
10883 int rc;
10901 rc = power_down_qam(demod, false);
10902 if (rc != 0) {
10903 pr_err("error %d\n", rc);
10909 rc = power_down_vsb(demod, false);
10910 if (rc != 0) {
10911 pr_err("error %d\n", rc);
10920 rc = -EINVAL;
10937 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10938 if (rc != 0) {
10939 pr_err("error %d\n", rc);
10946 rc = set_vsb_leak_n_gain(demod);
10947 if (rc != 0) {
10948 pr_err("error %d\n", rc);
10961 return rc;
11043 int rc;
11079 rc = power_up_device(demod);
11080 if (rc != 0) {
11081 pr_err("error %d\n", rc);
11107 rc = power_down_qam(demod, true);
11108 if (rc != 0) {
11109 pr_err("error %d\n", rc);
11114 rc = power_down_vsb(demod, true);
11115 if (rc != 0) {
11116 pr_err("error %d\n", rc);
11127 rc = power_down_atv(demod, ext_attr->standard, true);
11128 if (rc != 0) {
11129 pr_err("error %d\n", rc);
11144 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
11145 if (rc != 0) {
11146 pr_err("error %d\n", rc);
11149 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11150 if (rc != 0) {
11151 pr_err("error %d\n", rc);
11157 rc = init_hi(demod);
11158 if (rc != 0) {
11159 pr_err("error %d\n", rc);
11164 rc = hi_cfg_command(demod);
11165 if (rc != 0) {
11166 pr_err("error %d\n", rc);
11176 return rc;
11199 int rc;
11216 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11217 if (rc != 0) {
11218 pr_err("error %d\n", rc);
11241 return rc;
11262 int rc;
11297 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
11298 if (rc != 0) {
11299 pr_err("error %d\n", rc);
11322 return rc;
11355 int rc;
11374 rc = ctrl_power_mode(demod, &power_mode);
11375 if (rc != 0) {
11376 pr_err("error %d\n", rc);
11380 rc = -EINVAL;
11386 rc = get_device_capabilities(demod);
11387 if (rc != 0) {
11388 pr_err("error %d\n", rc);
11400 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
11401 if (rc != 0) {
11402 pr_err("error %d\n", rc);
11405 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11406 if (rc != 0) {
11407 pr_err("error %d\n", rc);
11414 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
11415 if (rc != 0) {
11416 pr_err("error %d\n", rc);
11420 rc = set_iqm_af(demod, false);
11421 if (rc != 0) {
11422 pr_err("error %d\n", rc);
11425 rc = set_orx_nsu_aox(demod, false);
11426 if (rc != 0) {
11427 pr_err("error %d\n", rc);
11431 rc = init_hi(demod);
11432 if (rc != 0) {
11433 pr_err("error %d\n", rc);
11441 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
11442 if (rc != 0) {
11443 pr_err("error %d\n", rc);
11447 rc = power_down_aud(demod);
11448 if (rc != 0) {
11449 pr_err("error %d\n", rc);
11453 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
11454 if (rc != 0) {
11455 pr_err("error %d\n", rc);
11468 rc = -EINVAL;
11472 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
11473 if (rc != 0) {
11474 pr_err("error %d while uploading the firmware\n", rc);
11478 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
11479 if (rc != 0) {
11481 rc);
11489 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11490 if (rc != 0) {
11491 pr_err("error %d\n", rc);
11502 rc = smart_ant_init(demod);
11503 if (rc != 0) {
11504 pr_err("error %d\n", rc);
11527 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
11528 if (rc != 0) {
11529 pr_err("error %d\n", rc);
11532 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
11533 if (rc != 0) {
11534 pr_err("error %d\n", rc);
11538 rc = ctrl_set_oob(demod, NULL);
11539 if (rc != 0) {
11540 pr_err("error %d\n", rc);
11552 return rc;
11565 int rc;
11576 rc = ctrl_power_mode(demod, &power_mode);
11577 if (rc != 0) {
11578 pr_err("error %d\n", rc);
11582 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11583 if (rc != 0) {
11584 pr_err("error %d\n", rc);
11588 rc = ctrl_power_mode(demod, &power_mode);
11589 if (rc != 0) {
11590 pr_err("error %d\n", rc);
11600 return rc;
11745 int rc;
11763 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
11764 if (rc < 0) {
11766 return rc;
11771 rc = -EINVAL;
11791 rc = -EINVAL;
11797 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
11798 if (rc)
11833 rc = -EINVAL;
11850 rc = -EIO;
11908 return rc;
12223 int rc = 0;
12228 rc = drxj_open(demod);
12229 if (rc != 0)
12230 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
12234 return rc;