Lines Matching refs:ext_attr
2235 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2240 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2244 hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2245 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2246 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2247 hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2248 hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2257 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2391 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2396 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2409 ext_attr->hi_cfg_timing_div =
2412 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
2413 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
2417 ext_attr->hi_cfg_bridge_delay =
2421 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
2422 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
2424 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
2429 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
2431 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
2433 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
2467 * * ext_attr->has_lna
2468 * * ext_attr->has_ntsc
2469 * * ext_attr->has_btsc
2470 * * ext_attr->has_oob
2476 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
2484 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2532 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
2553 ext_attr->has_lna = true;
2554 ext_attr->has_ntsc = false;
2555 ext_attr->has_btsc = false;
2556 ext_attr->has_oob = false;
2557 ext_attr->has_smatx = true;
2558 ext_attr->has_smarx = false;
2559 ext_attr->has_gpio = false;
2560 ext_attr->has_irqn = false;
2563 ext_attr->has_lna = false;
2564 ext_attr->has_ntsc = false;
2565 ext_attr->has_btsc = false;
2566 ext_attr->has_oob = false;
2567 ext_attr->has_smatx = true;
2568 ext_attr->has_smarx = false;
2569 ext_attr->has_gpio = false;
2570 ext_attr->has_irqn = false;
2573 ext_attr->has_lna = true;
2574 ext_attr->has_ntsc = true;
2575 ext_attr->has_btsc = false;
2576 ext_attr->has_oob = false;
2577 ext_attr->has_smatx = true;
2578 ext_attr->has_smarx = true;
2579 ext_attr->has_gpio = true;
2580 ext_attr->has_irqn = false;
2583 ext_attr->has_lna = false;
2584 ext_attr->has_ntsc = true;
2585 ext_attr->has_btsc = false;
2586 ext_attr->has_oob = false;
2587 ext_attr->has_smatx = true;
2588 ext_attr->has_smarx = true;
2589 ext_attr->has_gpio = true;
2590 ext_attr->has_irqn = false;
2593 ext_attr->has_lna = true;
2594 ext_attr->has_ntsc = true;
2595 ext_attr->has_btsc = true;
2596 ext_attr->has_oob = false;
2597 ext_attr->has_smatx = true;
2598 ext_attr->has_smarx = true;
2599 ext_attr->has_gpio = true;
2600 ext_attr->has_irqn = false;
2603 ext_attr->has_lna = false;
2604 ext_attr->has_ntsc = true;
2605 ext_attr->has_btsc = true;
2606 ext_attr->has_oob = false;
2607 ext_attr->has_smatx = true;
2608 ext_attr->has_smarx = true;
2609 ext_attr->has_gpio = true;
2610 ext_attr->has_irqn = false;
2613 ext_attr->has_lna = true;
2614 ext_attr->has_ntsc = false;
2615 ext_attr->has_btsc = false;
2616 ext_attr->has_oob = true;
2617 ext_attr->has_smatx = true;
2618 ext_attr->has_smarx = true;
2619 ext_attr->has_gpio = true;
2620 ext_attr->has_irqn = true;
2623 ext_attr->has_lna = false;
2624 ext_attr->has_ntsc = true;
2625 ext_attr->has_btsc = true;
2626 ext_attr->has_oob = true;
2627 ext_attr->has_smatx = true;
2628 ext_attr->has_smarx = true;
2629 ext_attr->has_gpio = true;
2630 ext_attr->has_irqn = true;
2633 ext_attr->has_lna = true;
2634 ext_attr->has_ntsc = true;
2635 ext_attr->has_btsc = true;
2636 ext_attr->has_oob = true;
2637 ext_attr->has_smatx = true;
2638 ext_attr->has_smarx = true;
2639 ext_attr->has_gpio = true;
2640 ext_attr->has_irqn = true;
2643 ext_attr->has_lna = false;
2644 ext_attr->has_ntsc = true;
2645 ext_attr->has_btsc = true;
2646 ext_attr->has_oob = true;
2647 ext_attr->has_smatx = true;
2648 ext_attr->has_smarx = true;
2649 ext_attr->has_gpio = true;
2650 ext_attr->has_irqn = true;
2731 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2753 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2759 switch (ext_attr->standard) {
2774 switch (ext_attr->standard) {
2821 switch (ext_attr->constellation) {
2839 } /* ext_attr->constellation */
2843 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2915 switch (ext_attr->standard) {
2921 switch (ext_attr->constellation) {
2943 } /* ext_attr->standard */
2950 switch (ext_attr->standard) {
2956 switch (ext_attr->constellation) {
2978 } /* ext_attr->standard */
3022 switch (ext_attr->standard) {
3035 if (ext_attr->curr_symbol_rate >=
3087 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
3088 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
3373 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3381 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3405 if (ext_attr->disable_te_ihandling) {
3446 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3452 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3463 if (ext_attr->bit_reverse_mpeg_outout)
3489 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3496 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3507 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
3537 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3543 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3555 if (!ext_attr->has_smatx)
3561 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3564 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3579 if (!ext_attr->has_smarx)
3584 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3587 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3602 if (!ext_attr->has_gpio)
3607 ext_attr->uio_gpio_mode = uio_cfg->mode;
3610 ext_attr->uio_gpio_mode = uio_cfg->mode;
3625 if (!ext_attr->has_irqn)
3629 ext_attr->uio_irqn_mode = uio_cfg->mode;
3638 ext_attr->uio_irqn_mode = uio_cfg->mode;
3672 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3680 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3692 if (!ext_attr->has_smatx)
3694 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
3695 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
3732 if (!ext_attr->has_smarx)
3734 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
3771 if (!ext_attr->has_gpio)
3773 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
3810 if (!ext_attr->has_irqn)
3813 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
3915 struct drxj_data *ext_attr = NULL;
3922 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3936 if (ext_attr->smart_ant_inverted) {
4388 struct drxj_data *ext_attr = NULL;
4410 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4412 switch (ext_attr->standard) {
4490 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
4491 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
4558 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
4559 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
4766 struct drxj_data *ext_attr = demod->my_ext_attr;
4782 rf_mirror = ext_attr->mirror == DRX_MIRROR_YES;
4788 switch (ext_attr->standard) {
4843 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
4844 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
4868 struct drxj_data *ext_attr = NULL;
4871 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4879 if (ext_attr->reset_pkt_err_acc) {
4882 ext_attr->reset_pkt_err_acc = false;
4914 struct drxj_data *ext_attr = NULL;
4923 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4934 if ((ext_attr->standard == agc_settings->standard) ||
4935 (DRXJ_ISQAMSTD(ext_attr->standard) &&
4937 (DRXJ_ISATVSTD(ext_attr->standard) &&
4964 if (ext_attr->standard == DRX_STANDARD_8VSB)
4966 else if (DRXJ_ISQAMSTD(ext_attr->standard))
4995 p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
4997 p_agc_settings = &(ext_attr->qam_if_agc_cfg);
4999 p_agc_settings = &(ext_attr->atv_if_agc_cfg);
5099 ext_attr->vsb_rf_agc_cfg = *agc_settings;
5105 ext_attr->qam_rf_agc_cfg = *agc_settings;
5128 struct drxj_data *ext_attr = NULL;
5137 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5148 if ((ext_attr->standard == agc_settings->standard) ||
5149 (DRXJ_ISQAMSTD(ext_attr->standard) &&
5151 (DRXJ_ISATVSTD(ext_attr->standard) &&
5178 if (ext_attr->standard == DRX_STANDARD_8VSB)
5180 else if (DRXJ_ISQAMSTD(ext_attr->standard))
5209 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
5211 p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
5213 p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
5328 ext_attr->vsb_if_agc_cfg = *agc_settings;
5334 ext_attr->qam_if_agc_cfg = *agc_settings;
5719 struct drxj_data *ext_attr = NULL;
5755 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5822 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
5823 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
6039 if (!ext_attr->has_lna) {
6064 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6069 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6079 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
6086 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6467 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6478 struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */
6492 ext_attr = (struct drxj_data *) demod->my_ext_attr;
6494 fec_bits_desired = ext_attr->fec_bits_desired;
6495 fec_rs_prescale = ext_attr->fec_rs_prescale;
6523 /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
6524 switch (ext_attr->standard) {
6536 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */
6543 if (ext_attr->standard != DRX_STANDARD_ITU_B)
6551 switch (ext_attr->standard) {
6588 ext_attr->fec_rs_period = (u16) fec_rs_period;
6589 ext_attr->fec_rs_prescale = fec_rs_prescale;
6606 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
6615 fec_vd_plen = ext_attr->fec_vd_plen;
6616 qam_vd_prescale = ext_attr->qam_vd_prescale;
6657 ext_attr->qam_vd_period = (u16) qam_vd_period;
6658 ext_attr->qam_vd_prescale = qam_vd_prescale;
7859 struct drxj_data *ext_attr = NULL;
7997 ext_attr = (struct drxj_data *) demod->my_ext_attr;
8001 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8041 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8045 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8049 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8149 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
8183 if (!ext_attr->has_lna) {
8264 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8470 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8475 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8485 qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
8492 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8500 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8511 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8540 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8677 struct drxj_data *ext_attr = demod->my_ext_attr;
8767 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
8768 ext_attr->pos_image = !ext_attr->pos_image;
8871 struct drxj_data *ext_attr = demod->my_ext_attr;
8942 ext_attr->mirror = DRX_MIRROR_YES;
9019 struct drxj_data *ext_attr = demod->my_ext_attr;
9059 ext_attr->mirror = DRX_MIRROR_YES;
9100 struct drxj_data *ext_attr = NULL;
9106 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9116 if (ext_attr->standard != DRX_STANDARD_ITU_B)
9119 ext_attr->constellation = channel->constellation;
9121 ext_attr->mirror = DRX_MIRROR_NO;
9123 ext_attr->mirror = channel->mirror;
9143 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9150 ext_attr->constellation = DRX_CONSTELLATION_QAM256;
9152 ext_attr->mirror = DRX_MIRROR_NO;
9154 ext_attr->mirror = channel->mirror;
9175 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9177 ext_attr->mirror = DRX_MIRROR_NO;
9179 ext_attr->mirror = channel->mirror;
9225 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
9229 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9233 ext_attr->mirror = DRX_MIRROR_NO;
9235 ext_attr->mirror = channel->mirror;
9463 struct drxj_data *ext_attr = demod->my_ext_attr;
9467 enum drx_modulation constellation = ext_attr->constellation;
9517 fec_rs_period = ext_attr->fec_rs_period;
9518 fec_rs_prescale = ext_attr->fec_rs_prescale;
9519 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
9520 qam_vd_period = ext_attr->qam_vd_period;
9521 qam_vd_prescale = ext_attr->qam_vd_prescale;
9522 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
9633 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9844 struct drxj_data *ext_attr = NULL;
9848 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9856 ext_attr->aud_data.audio_is_active = false;
9926 struct drxj_data *ext_attr = NULL;
9949 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9950 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
9976 ext_attr->oob_power_on = false;
9988 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
10152 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10408 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10414 ext_attr->oob_power_on = true;
10448 struct drxj_data *ext_attr = NULL;
10462 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10463 standard = ext_attr->standard;
10585 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
10623 ext_attr->mirror = DRX_MIRROR_NO;
10625 ext_attr->mirror = channel->mirror;
10654 ext_attr->reset_pkt_err_acc = true;
10681 struct drxj_data *ext_attr = demod->my_ext_attr;
10684 enum drx_standard standard = ext_attr->standard;
10793 struct drxj_data *ext_attr = NULL;
10810 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10811 standard = ext_attr->standard;
10882 struct drxj_data *ext_attr = NULL;
10890 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10891 prev_standard = ext_attr->standard;
10928 ext_attr->standard = *standard;
10953 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10960 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10966 static void drxj_reset_mode(struct drxj_data *ext_attr)
10969 if (ext_attr->has_lna) {
10972 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10973 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10974 ext_attr->qam_pga_cfg = 140 + (11 * 13);
10976 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10977 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10978 ext_attr->vsb_pga_cfg = 140 + (11 * 13);
10982 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10983 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10984 ext_attr->qam_if_agc_cfg.min_output_level = 0;
10985 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
10986 ext_attr->qam_if_agc_cfg.speed = 3;
10987 ext_attr->qam_if_agc_cfg.top = 1297;
10988 ext_attr->qam_pga_cfg = 140;
10990 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10991 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10992 ext_attr->vsb_if_agc_cfg.min_output_level = 0;
10993 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
10994 ext_attr->vsb_if_agc_cfg.speed = 3;
10995 ext_attr->vsb_if_agc_cfg.top = 1024;
10996 ext_attr->vsb_pga_cfg = 140;
11001 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
11002 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11003 ext_attr->qam_rf_agc_cfg.min_output_level = 0;
11004 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
11005 ext_attr->qam_rf_agc_cfg.speed = 3;
11006 ext_attr->qam_rf_agc_cfg.top = 9500;
11007 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
11008 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
11009 ext_attr->qam_pre_saw_cfg.reference = 0x07;
11010 ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
11013 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
11014 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11015 ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
11016 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
11017 ext_attr->vsb_rf_agc_cfg.speed = 3;
11018 ext_attr->vsb_rf_agc_cfg.top = 9500;
11019 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
11020 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
11021 ext_attr->vsb_pre_saw_cfg.reference = 0x07;
11022 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
11041 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
11047 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11090 drxj_reset_mode(ext_attr);
11103 switch (ext_attr->standard) {
11127 rc = power_down_atv(demod, ext_attr->standard, true);
11140 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11163 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
11198 struct drxj_data *ext_attr = NULL;
11202 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11211 if ((ext_attr->standard == pre_saw->standard) ||
11212 (DRXJ_ISQAMSTD(ext_attr->standard) &&
11214 (DRXJ_ISATVSTD(ext_attr->standard) &&
11226 ext_attr->vsb_pre_saw_cfg = *pre_saw;
11232 ext_attr->qam_pre_saw_cfg = *pre_saw;
11261 struct drxj_data *ext_attr = NULL;
11270 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11296 if (ext_attr->standard == afe_gain->standard) {
11307 ext_attr->vsb_pga_cfg = gain * 13 + 140;
11313 ext_attr->qam_pga_cfg = gain * 13 + 140;
11350 struct drxj_data *ext_attr = NULL;
11371 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11499 drxj_reset_mode(ext_attr);
11500 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11545 ext_attr->aud_data = drxj_default_aud_data_g;
12242 struct drxj_data *ext_attr = demod->my_ext_attr;
12245 if (!ext_attr->has_lna) {