media/dvb-frontends/dib7000m.c

316 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw)
320 	if (!bw)
321 		bw = 8000;
324 	state->current_bandwidth = bw;
334 	timf = timf * (bw / 50) / 160;
382 static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw)
384 	dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
385 	dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000)        & 0xffff));
386 	dib7000m_write_word(state, 21, (u16) ( (bw->ifreq          >> 16) & 0xffff));
387 	dib7000m_write_word(state, 22, (u16) (  bw->ifreq                 & 0xffff));
389 	dib7000m_write_word(state, 928, bw->sad_cfg);
394 	const struct dibx000_bandwidth_config *bw = state->cfg.bw;
398 	reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) |
399 		(bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) |
400 		(bw->enable_refdiv << 1) | (0 << 0);
401 	reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset;
414 		reg_907 |= (bw->pll_ratio & 0x3f) << 9;
415 		reg_910 |= (bw->pll_prediv << 5);
422 	dib7000m_reset_pll_common(state, bw);
427 	const struct dibx000_bandwidth_config *bw = state->cfg.bw;
431 	dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
436 			(bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) |
437 			(1 << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0);
439 	clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3);
443 	dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));
445 	dib7000m_reset_pll_common(state, bw);
626 	state->internal_clk = state->cfg.bw->internal;
1419 	st->timf_default = cfg->bw->timf;