Lines Matching refs:state
53 static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg)
56 { .addr = state->i2c_addr >> 1, .flags = 0, .len = 2 },
57 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .len = 2 },
74 if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
83 static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val)
86 .addr = state->i2c_addr >> 1, .flags = 0, .len = 4
102 rc = i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
108 static int dib3000mc_identify(struct dib3000mc_state *state)
111 if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) {
116 value = dib3000mc_read_word(state, 1026);
121 state->dev_id = value;
123 dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id);
128 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset)
132 if (state->timf == 0) {
137 timf = state->timf;
142 s16 tim_offs = dib3000mc_read_word(state, 416);
151 state->timf = timf / (bw / 1000);
156 dib3000mc_write_word(state, 23, (u16) (timf >> 16));
157 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff);
162 static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state)
164 u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb;
165 if (state->cfg->pwm3_inversion) {
172 dib3000mc_write_word(state, 51, reg_51);
173 dib3000mc_write_word(state, 52, reg_52);
175 if (state->cfg->use_pwm3)
176 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0));
178 dib3000mc_write_word(state, 245, 0);
180 dib3000mc_write_word(state, 1040, 0x3);
184 static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode)
191 u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */
194 &state->demod, mode);
228 dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod);
233 if ((state->cfg->output_mpeg2_in_188_bytes))
236 outreg = dib3000mc_read_word(state, 244) & 0x07FF;
238 ret |= dib3000mc_write_word(state, 244, outreg);
239 ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/
240 ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */
241 ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */
245 static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw)
277 dib3000mc_write_word(state, reg, bw_cfg[reg - 6]);
278 dib3000mc_write_word(state, 12, 0x0000);
279 dib3000mc_write_word(state, 13, 0x03e8);
280 dib3000mc_write_word(state, 14, 0x0000);
281 dib3000mc_write_word(state, 15, 0x03f2);
282 dib3000mc_write_word(state, 16, 0x0001);
283 dib3000mc_write_word(state, 17, 0xb0d0);
285 dib3000mc_write_word(state, 18, 0x0393);
286 dib3000mc_write_word(state, 19, 0x8700);
289 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);
292 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);
305 static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft)
309 dib3000mc_write_word(state, i, impulse_noise_val[i-58]);
312 dib3000mc_write_word(state, 58, 0x3b);
313 dib3000mc_write_word(state, 84, 0x00);
314 dib3000mc_write_word(state, 85, 0x8200);
317 dib3000mc_write_word(state, 34, 0x1294);
318 dib3000mc_write_word(state, 35, 0x1ff8);
320 dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10));
325 struct dib3000mc_state *state = demod->demodulator_priv;
326 struct dibx000_agc_config *agc = state->cfg->agc;
329 dib3000mc_write_word(state, 1027, 0x8000);
330 dib3000mc_write_word(state, 1027, 0x0000);
333 dib3000mc_write_word(state, 140, 0x0000);
334 dib3000mc_write_word(state, 1031, 0);
336 if (state->cfg->mobile_mode) {
337 dib3000mc_write_word(state, 139, 0x0000);
338 dib3000mc_write_word(state, 141, 0x0000);
339 dib3000mc_write_word(state, 175, 0x0002);
340 dib3000mc_write_word(state, 1032, 0x0000);
342 dib3000mc_write_word(state, 139, 0x0001);
343 dib3000mc_write_word(state, 141, 0x0000);
344 dib3000mc_write_word(state, 175, 0x0000);
345 dib3000mc_write_word(state, 1032, 0x012C);
347 dib3000mc_write_word(state, 1033, 0x0000);
350 dib3000mc_write_word(state, 1037, 0x3130);
355 dib3000mc_write_word(state, 33, (5 << 0));
356 dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0));
360 dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0));
362 if (state->cfg->phase_noise_mode == 0)
363 dib3000mc_write_word(state, 111, 0x00);
365 dib3000mc_write_word(state, 111, 0x02);
368 dib3000mc_write_word(state, 50, 0x8000);
371 dib3000mc_setup_pwm_state(state);
374 dib3000mc_write_word(state, 53, 0x87);
376 dib3000mc_write_word(state, 54, 0x87);
379 dib3000mc_write_word(state, 36, state->cfg->max_time);
380 dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0));
381 dib3000mc_write_word(state, 38, state->cfg->pwm3_value);
382 dib3000mc_write_word(state, 39, state->cfg->ln_adc_level);
385 dib3000mc_write_word(state, 40, 0x0179);
386 dib3000mc_write_word(state, 41, 0x03f0);
388 dib3000mc_write_word(state, 42, agc->agc1_max);
389 dib3000mc_write_word(state, 43, agc->agc1_min);
390 dib3000mc_write_word(state, 44, agc->agc2_max);
391 dib3000mc_write_word(state, 45, agc->agc2_min);
392 dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
393 dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
394 dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
395 dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
399 dib3000mc_write_word(state, 110, 3277);
401 dib3000mc_write_word(state, 26, 0x6680);
403 dib3000mc_write_word(state, 1, 4);
405 dib3000mc_write_word(state, 2, 4);
407 dib3000mc_write_word(state, 3, 0x1000);
409 dib3000mc_write_word(state, 5, 1);
411 dib3000mc_set_bandwidth(state, 8000);
414 dib3000mc_write_word(state, 4, 0x814);
416 dib3000mc_write_word(state, 21, (1 << 9) | 0x164);
417 dib3000mc_write_word(state, 22, 0x463d);
421 dib3000mc_write_word(state, 120, 0x200f);
423 dib3000mc_write_word(state, 134, 0);
426 dib3000mc_write_word(state, 195, 0x10);
429 dib3000mc_write_word(state, 180, 0x2FF0);
432 dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K);
435 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
438 dib3000mc_write_word(state, 769, (1 << 7) );
445 struct dib3000mc_state *state = demod->demodulator_priv;
447 dib3000mc_write_word(state, 1031, 0xFFFF);
448 dib3000mc_write_word(state, 1032, 0xFFFF);
449 dib3000mc_write_word(state, 1033, 0xFFF0);
454 static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam)
469 dib3000mc_write_word(state, reg, cfg[reg - 129]);
472 static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state,
478 dib3000mc_set_bandwidth(state, bw);
479 dib3000mc_set_timing(state, ch->transmission_mode, bw, 0);
482 dib3000mc_write_word(state, 100, (16 << 6) + 9);
485 dib3000mc_write_word(state, 100, (11 << 6) + 6);
487 dib3000mc_write_word(state, 100, (16 << 6) + 9);
490 dib3000mc_write_word(state, 1027, 0x0800);
491 dib3000mc_write_word(state, 1027, 0x0000);
494 dib3000mc_write_word(state, 26, 0x6680);
495 dib3000mc_write_word(state, 29, 0x1273);
496 dib3000mc_write_word(state, 33, 5);
497 dib3000mc_set_adp_cfg(state, QAM_16);
498 dib3000mc_write_word(state, 133, 15564);
500 dib3000mc_write_word(state, 12 , 0x0);
501 dib3000mc_write_word(state, 13 , 0x3e8);
502 dib3000mc_write_word(state, 14 , 0x0);
503 dib3000mc_write_word(state, 15 , 0x3f2);
505 dib3000mc_write_word(state, 93,0);
506 dib3000mc_write_word(state, 94,0);
507 dib3000mc_write_word(state, 95,0);
508 dib3000mc_write_word(state, 96,0);
509 dib3000mc_write_word(state, 97,0);
510 dib3000mc_write_word(state, 98,0);
512 dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode);
539 dib3000mc_write_word(state, 0, value);
540 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
555 dib3000mc_write_word(state, 181, value);
571 value |= dib3000mc_read_word(state, 180) & 0x000f;
572 dib3000mc_write_word(state, 180, value);
575 value = dib3000mc_read_word(state, 0);
576 dib3000mc_write_word(state, 0, value | (1 << 9));
577 dib3000mc_write_word(state, 0, value);
581 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode);
587 struct dib3000mc_state *state = demod->demodulator_priv;
604 dib3000mc_set_channel_cfg(state, &schan, 11);
606 reg = dib3000mc_read_word(state, 0);
607 dib3000mc_write_word(state, 0, reg | (1 << 8));
608 dib3000mc_read_word(state, 511);
609 dib3000mc_write_word(state, 0, reg);
616 struct dib3000mc_state *state = demod->demodulator_priv;
617 u16 irq_pending = dib3000mc_read_word(state, 511);
631 struct dib3000mc_state *state = demod->demodulator_priv;
634 dib3000mc_set_channel_cfg(state, ch, 0);
637 if (state->sfn_workaround_active) {
639 dib3000mc_write_word(state, 29, 0x1273);
640 dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift
642 dib3000mc_write_word(state, 29, 0x1073);
643 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift
646 dib3000mc_set_adp_cfg(state, (u8)ch->modulation);
648 dib3000mc_write_word(state, 26, 38528);
649 dib3000mc_write_word(state, 33, 8);
651 dib3000mc_write_word(state, 26, 30336);
652 dib3000mc_write_word(state, 33, 6);
655 if (dib3000mc_read_word(state, 509) & 0x80)
656 dib3000mc_set_timing(state, ch->transmission_mode,
673 struct dib3000mc_state *state = fe->demodulator_priv;
674 u16 tps = dib3000mc_read_word(state,458);
678 fep->bandwidth_hz = state->current_bandwidth;
728 struct dib3000mc_state *state = fe->demodulator_priv;
731 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
733 state->current_bandwidth = fep->bandwidth_hz;
734 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
737 state->sfn_workaround_active = buggy_sfn_workaround;
766 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);
772 struct dib3000mc_state *state = fe->demodulator_priv;
773 u16 lock = dib3000mc_read_word(state, 509);
793 struct dib3000mc_state *state = fe->demodulator_priv;
794 *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501);
800 struct dib3000mc_state *state = fe->demodulator_priv;
801 *unc = dib3000mc_read_word(state, 508);
807 struct dib3000mc_state *state = fe->demodulator_priv;
808 u16 val = dib3000mc_read_word(state, 392);
827 struct dib3000mc_state *state = fe->demodulator_priv;
828 dibx000_exit_i2c_master(&state->i2c_master);
829 kfree(state);
834 struct dib3000mc_state *state = fe->demodulator_priv;
835 dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0);
842 struct dib3000mc_state *state = fe->demodulator_priv;
843 u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4);
845 return dib3000mc_write_word(state, 206, tmp);
851 struct dib3000mc_state *state = fe->demodulator_priv;
852 state->cfg = cfg;