Lines Matching refs:ci
53 static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
57 if (ci->lastaddress != adr)
58 status = regmap_write(ci->regmap, 0, adr);
60 ci->lastaddress = adr;
65 if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
66 len = ci->cfg.max_i2c;
67 status = regmap_raw_read(ci->regmap, 1, data, len);
77 static int read_reg(struct cxd *ci, u8 reg, u8 *val)
79 return read_block(ci, reg, val, 1);
82 static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
87 status = regmap_raw_write(ci->regmap, 2, addr, 2);
89 status = regmap_raw_read(ci->regmap, 3, data, n);
93 static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
98 status = regmap_raw_write(ci->regmap, 2, addr, 2);
103 status = regmap_raw_write(ci->regmap, 3, buf, n);
108 static int read_io(struct cxd *ci, u16 address, unsigned int *val)
113 status = regmap_raw_write(ci->regmap, 2, addr, 2);
115 status = regmap_read(ci->regmap, 3, val);
119 static int write_io(struct cxd *ci, u16 address, u8 val)
124 status = regmap_raw_write(ci->regmap, 2, addr, 2);
126 status = regmap_write(ci->regmap, 3, val);
130 static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
135 if (ci->lastaddress != reg)
136 status = regmap_write(ci->regmap, 0, reg);
138 status = regmap_read(ci->regmap, 1, ®val);
139 ci->regs[reg] = regval;
141 ci->lastaddress = reg;
142 ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
144 status = regmap_write(ci->regmap, 1, ci->regs[reg]);
146 ci->regs[reg] &= 0x7f;
150 static int write_reg(struct cxd *ci, u8 reg, u8 val)
152 return write_regm(ci, reg, val, 0xff);
155 static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
158 u8 *buf = ci->wbuf;
160 if (ci->lastaddress != adr)
161 status = regmap_write(ci->regmap, 0, adr);
165 ci->lastaddress = adr;
169 if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
170 len = ci->cfg.max_i2c - 1;
172 status = regmap_raw_write(ci->regmap, 1, buf, len);
181 static void set_mode(struct cxd *ci, int mode)
183 if (mode == ci->mode)
188 write_regm(ci, 0x06, 0x00, 0x07);
191 write_regm(ci, 0x06, 0x02, 0x07);
196 ci->mode = mode;
199 static void cam_mode(struct cxd *ci, int mode)
203 if (mode == ci->cammode)
208 write_regm(ci, 0x20, 0x80, 0x80);
211 if (!ci->en.read_data)
213 ci->write_busy = 0;
214 dev_info(&ci->client->dev, "enable cam buffer mode\n");
215 write_reg(ci, 0x0d, 0x00);
216 write_reg(ci, 0x0e, 0x01);
217 write_regm(ci, 0x08, 0x40, 0x40);
218 read_reg(ci, 0x12, &dummy);
219 write_regm(ci, 0x08, 0x80, 0x80);
224 ci->cammode = mode;
227 static int init(struct cxd *ci)
231 mutex_lock(&ci->lock);
232 ci->mode = -1;
234 status = write_reg(ci, 0x00, 0x00);
237 status = write_reg(ci, 0x01, 0x00);
240 status = write_reg(ci, 0x02, 0x10);
243 status = write_reg(ci, 0x03, 0x00);
246 status = write_reg(ci, 0x05, 0xFF);
249 status = write_reg(ci, 0x06, 0x1F);
252 status = write_reg(ci, 0x07, 0x1F);
255 status = write_reg(ci, 0x08, 0x28);
258 status = write_reg(ci, 0x14, 0x20);
265 status = write_reg(ci, 0x0A, 0xA7);
269 status = write_reg(ci, 0x0B, 0x33);
272 status = write_reg(ci, 0x0C, 0x33);
276 status = write_regm(ci, 0x14, 0x00, 0x0F);
279 status = write_reg(ci, 0x15, ci->clk_reg_b);
282 status = write_regm(ci, 0x16, 0x00, 0x0F);
285 status = write_reg(ci, 0x17, ci->clk_reg_f);
289 if (ci->cfg.clock_mode == 2) {
291 u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
293 if (ci->cfg.polarity) {
294 status = write_reg(ci, 0x09, 0x6f);
298 status = write_reg(ci, 0x09, 0x6d);
302 status = write_reg(ci, 0x20, 0x08);
305 status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
308 status = write_reg(ci, 0x22, reg & 0xff);
311 } else if (ci->cfg.clock_mode == 1) {
312 if (ci->cfg.polarity) {
313 status = write_reg(ci, 0x09, 0x6f); /* D */
317 status = write_reg(ci, 0x09, 0x6d);
321 status = write_reg(ci, 0x20, 0x68);
324 status = write_reg(ci, 0x21, 0x00);
327 status = write_reg(ci, 0x22, 0x02);
331 if (ci->cfg.polarity) {
332 status = write_reg(ci, 0x09, 0x4f); /* C */
336 status = write_reg(ci, 0x09, 0x4d);
340 status = write_reg(ci, 0x20, 0x28);
343 status = write_reg(ci, 0x21, 0x00);
346 status = write_reg(ci, 0x22, 0x07);
351 status = write_regm(ci, 0x20, 0x80, 0x80);
354 status = write_regm(ci, 0x03, 0x02, 0x02);
357 status = write_reg(ci, 0x01, 0x04);
360 status = write_reg(ci, 0x00, 0x31);
365 status = write_regm(ci, 0x09, 0x08, 0x08);
368 ci->cammode = -1;
369 cam_mode(ci, 0);
371 mutex_unlock(&ci->lock);
379 struct cxd *ci = ca->data;
382 mutex_lock(&ci->lock);
383 set_mode(ci, 1);
384 read_pccard(ci, address, &val, 1);
385 mutex_unlock(&ci->lock);
392 struct cxd *ci = ca->data;
394 mutex_lock(&ci->lock);
395 set_mode(ci, 1);
396 write_pccard(ci, address, &value, 1);
397 mutex_unlock(&ci->lock);
404 struct cxd *ci = ca->data;
407 mutex_lock(&ci->lock);
408 set_mode(ci, 0);
409 read_io(ci, address, &val);
410 mutex_unlock(&ci->lock);
417 struct cxd *ci = ca->data;
419 mutex_lock(&ci->lock);
420 set_mode(ci, 0);
421 write_io(ci, address, value);
422 mutex_unlock(&ci->lock);
428 struct cxd *ci = ca->data;
430 if (ci->cammode)
431 read_data(ca, slot, ci->rbuf, 0);
433 mutex_lock(&ci->lock);
434 cam_mode(ci, 0);
435 write_reg(ci, 0x00, 0x21);
436 write_reg(ci, 0x06, 0x1F);
437 write_reg(ci, 0x00, 0x31);
438 write_regm(ci, 0x20, 0x80, 0x80);
439 write_reg(ci, 0x03, 0x02);
440 ci->ready = 0;
441 ci->mode = -1;
447 if (ci->ready)
451 mutex_unlock(&ci->lock);
457 struct cxd *ci = ca->data;
459 dev_dbg(&ci->client->dev, "%s\n", __func__);
460 if (ci->cammode)
461 read_data(ca, slot, ci->rbuf, 0);
462 mutex_lock(&ci->lock);
463 write_reg(ci, 0x00, 0x21);
464 write_reg(ci, 0x06, 0x1F);
467 write_regm(ci, 0x09, 0x08, 0x08);
468 write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
469 write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
471 ci->mode = -1;
472 ci->write_busy = 0;
473 mutex_unlock(&ci->lock);
479 struct cxd *ci = ca->data;
481 mutex_lock(&ci->lock);
482 write_regm(ci, 0x09, 0x00, 0x08);
483 set_mode(ci, 0);
484 cam_mode(ci, 1);
485 mutex_unlock(&ci->lock);
489 static int campoll(struct cxd *ci)
493 read_reg(ci, 0x04, &istat);
496 write_reg(ci, 0x05, istat);
499 ci->dr = 1;
501 ci->write_busy = 0;
506 read_reg(ci, 0x01, &slotstat);
508 if (!ci->slot_stat) {
509 ci->slot_stat |=
511 write_regm(ci, 0x03, 0x08, 0x08);
515 if (ci->slot_stat) {
516 ci->slot_stat = 0;
517 write_regm(ci, 0x03, 0x00, 0x08);
518 dev_info(&ci->client->dev, "NO CAM\n");
519 ci->ready = 0;
523 ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
524 ci->ready = 1;
525 ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
533 struct cxd *ci = ca->data;
536 mutex_lock(&ci->lock);
537 campoll(ci);
538 read_reg(ci, 0x01, &slotstat);
539 mutex_unlock(&ci->lock);
541 return ci->slot_stat;
546 struct cxd *ci = ca->data;
550 mutex_lock(&ci->lock);
551 campoll(ci);
552 mutex_unlock(&ci->lock);
554 if (!ci->dr)
557 mutex_lock(&ci->lock);
558 read_reg(ci, 0x0f, &msb);
559 read_reg(ci, 0x10, &lsb);
563 read_block(ci, 0x12, ci->rbuf, len);
564 mutex_unlock(&ci->lock);
567 read_block(ci, 0x12, ebuf, len);
568 ci->dr = 0;
569 mutex_unlock(&ci->lock);
575 struct cxd *ci = ca->data;
577 if (ci->write_busy)
579 mutex_lock(&ci->lock);
580 write_reg(ci, 0x0d, ecount >> 8);
581 write_reg(ci, 0x0e, ecount & 0xff);
582 write_block(ci, 0x11, ebuf, ecount);
583 ci->write_busy = 1;
584 mutex_unlock(&ci->lock);
603 struct cxd *ci;
612 ci = kzalloc(sizeof(*ci), GFP_KERNEL);
613 if (!ci) {
618 ci->client = client;
619 memcpy(&ci->cfg, cfg, sizeof(ci->cfg));
621 ci->regmap = regmap_init_i2c(client, &rm_cfg);
622 if (IS_ERR(ci->regmap)) {
623 ret = PTR_ERR(ci->regmap);
627 ret = regmap_read(ci->regmap, 0x00, &val);
634 mutex_init(&ci->lock);
635 ci->lastaddress = 0xff;
636 ci->clk_reg_b = 0x4a;
637 ci->clk_reg_f = 0x1b;
639 ci->en = en_templ;
640 ci->en.data = ci;
641 init(ci);
644 *cfg->en = &ci->en;
647 ci->en.read_data = NULL;
648 ci->en.write_data = NULL;
653 i2c_set_clientdata(client, ci);
658 regmap_exit(ci->regmap);
660 kfree(ci);
668 struct cxd *ci = i2c_get_clientdata(client);
670 regmap_exit(ci->regmap);
671 kfree(ci);