platform/s5p/exynos_hdmi_cecctrl.c

26 	unsigned int reg;
30 	if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, &reg)) {
35 	reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16);
37 	if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) {
44 	writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3);
45 	writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2);
46 	writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1);
47 	writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0);
52 	u8 reg;
54 	reg = readb(cec->reg + S5P_CEC_RX_CTRL);
55 	reg |= S5P_CEC_RX_CTRL_ENABLE;
56 	writeb(reg, cec->reg + S5P_CEC_RX_CTRL);
61 	u8 reg;
63 	reg = readb(cec->reg + S5P_CEC_IRQ_MASK);
64 	reg |= S5P_CEC_IRQ_RX_DONE;
65 	reg |= S5P_CEC_IRQ_RX_ERROR;
66 	writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);
71 	u8 reg;
73 	reg = readb(cec->reg + S5P_CEC_IRQ_MASK);
74 	reg &= ~S5P_CEC_IRQ_RX_DONE;
75 	reg &= ~S5P_CEC_IRQ_RX_ERROR;
76 	writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);
81 	u8 reg;
83 	reg = readb(cec->reg + S5P_CEC_IRQ_MASK);
84 	reg |= S5P_CEC_IRQ_TX_DONE;
85 	reg |= S5P_CEC_IRQ_TX_ERROR;
86 	writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);
91 	u8 reg;
93 	reg = readb(cec->reg + S5P_CEC_IRQ_MASK);
94 	reg &= ~S5P_CEC_IRQ_TX_DONE;
95 	reg &= ~S5P_CEC_IRQ_TX_ERROR;
96 	writeb(reg, cec->reg + S5P_CEC_IRQ_MASK);
101 	u8 reg;
103 	writeb(S5P_CEC_RX_CTRL_RESET, cec->reg + S5P_CEC_RX_CTRL);
104 	writeb(S5P_CEC_TX_CTRL_RESET, cec->reg + S5P_CEC_TX_CTRL);
106 	reg = readb(cec->reg + 0xc4);
107 	reg &= ~0x1;
108 	writeb(reg, cec->reg + 0xc4);
113 	writeb(S5P_CEC_TX_CTRL_RESET, cec->reg + S5P_CEC_TX_CTRL);
118 	u8 reg;
120 	writeb(S5P_CEC_RX_CTRL_RESET, cec->reg + S5P_CEC_RX_CTRL);
122 	reg = readb(cec->reg + 0xc4);
123 	reg &= ~0x1;
124 	writeb(reg, cec->reg + 0xc4);
129 	writeb(CEC_FILTER_THRESHOLD, cec->reg + S5P_CEC_RX_FILTER_TH);
130 	writeb(0, cec->reg + S5P_CEC_RX_FILTER_CTRL);
137 	u8 reg;
140 		writeb(data[i], cec->reg + (S5P_CEC_TX_BUFF0 + (i * 4)));
144 	writeb(count, cec->reg + S5P_CEC_TX_BYTES);
145 	reg = readb(cec->reg + S5P_CEC_TX_CTRL);
146 	reg |= S5P_CEC_TX_CTRL_START;
147 	reg &= ~0x70;
148 	reg |= retries << 4;
152 		reg |= S5P_CEC_TX_CTRL_BCAST;
155 		reg &= ~S5P_CEC_TX_CTRL_BCAST;
158 	writeb(reg, cec->reg + S5P_CEC_TX_CTRL);
165 	writeb(addr & 0x0F, cec->reg + S5P_CEC_LOGIC_ADDR);
172 	status = readb(cec->reg + S5P_CEC_STATUS_0) & 0xf;
173 	status |= (readb(cec->reg + S5P_CEC_TX_STAT1) & 0xf) << 4;
174 	status |= readb(cec->reg + S5P_CEC_STATUS_1) << 8;
175 	status |= readb(cec->reg + S5P_CEC_STATUS_2) << 16;
176 	status |= readb(cec->reg + S5P_CEC_STATUS_3) << 24;
186 	       cec->reg + S5P_CEC_IRQ_CLEAR);
192 	       cec->reg + S5P_CEC_IRQ_CLEAR);
201 		buffer[i] = readb(cec->reg + S5P_CEC_RX_BUFF0 + (i * 4));