drivers/mailbox/imx-mailbox.c

82 	enum imx_mu_chan_type	type;
120 	enum imx_mu_type type;
127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
132 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
134 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
136 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
138 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
140 #define IMX_MU_xCR_RST(type)	(type & IMX_MU_V2 ? BIT(0) : BIT(5))
141 #define IMX_MU_xSR_RST(type)	(type & IMX_MU_V2 ? BIT(0) : BIT(7))
169 		can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
193 		can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
208 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
214 	val = imx_mu_read(priv, priv->dcfg->xCR[type]);
217 	imx_mu_write(priv, val, priv->dcfg->xCR[type]);
229 	switch (cp->type) {
232 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
235 		imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
239 		imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
242 		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
263 	imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
278 	if (priv->dcfg->type & IMX_MU_V2_S4) {
286 	switch (cp->type) {
307 						 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
316 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
319 		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
336 	imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
339 	if (priv->dcfg->type & IMX_MU_V2_S4) {
354 					 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0,
363 	imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
380 	switch (cp->type) {
404 			       IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
429 				     "Send data on wrong channel type: %d\n",
430 				     cp->type);
469 	imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
502 	switch (cp->type) {
506 		val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
507 			(ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
512 		val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
513 			(ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
518 		val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
519 			(ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
524 		dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
525 				     cp->type);
532 	if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
533 	    (cp->type == IMX_MU_TYPE_TX)) {
534 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
536 	} else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
537 		   (cp->type == IMX_MU_TYPE_RX)) {
539 	} else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
540 		   (cp->type == IMX_MU_TYPE_RXDB)) {
569 	if (cp->type == IMX_MU_TYPE_TXDB_V2)
572 	if (cp->type == IMX_MU_TYPE_TXDB) {
582 	if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
585 	ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);
587 		dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);
591 	switch (cp->type) {
593 		imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
596 		imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
612 	if (cp->type == IMX_MU_TYPE_TXDB_V2) {
617 	if (cp->type == IMX_MU_TYPE_TXDB) {
623 	switch (cp->type) {
625 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
628 		imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
631 		imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
634 		imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
636 					 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
644 	free_irq(priv->irq[cp->type], chan);
657 	u32 type, idx, chan;
664 	type = sp->args[0]; /* channel type */
667 	switch (type) {
672 		chan = type;
678 		dev_err(mbox->dev, "Invalid chan type: %d\n", type);
683 		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
694 	u32 type, idx, chan;
701 	type = sp->args[0]; /* channel type */
705 	if ((type == IMX_MU_TYPE_RST) && idx) {
710 	chan = type * 4 + idx;
712 		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
718 	if (type == IMX_MU_TYPE_TXDB_V2)
727 	u32 type;
734 	type = sp->args[0]; /* channel type */
737 	if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
738 		dev_err(mbox->dev, "Invalid type: %d\n", type);
749 	if (priv->dcfg->type & IMX_MU_V2) {
773 		cp->type = i >> 2;
777 			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
804 	int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
810 		cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
814 			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
862 	if (priv->dcfg->type & IMX_MU_V2_IRQ) {
878 	if (priv->dcfg->type & IMX_MU_V2_S4)
981 	.type	= IMX_MU_V2,
992 	.type	= IMX_MU_V2 | IMX_MU_V2_S4,
1003 	.type	= IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ,