drivers/mailbox/armada-37xx-rwtm-mailbox.c

45 	struct a37xx_mbox *mbox = chan->con_priv;
49 	rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS);
51 		rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i));
59 	struct a37xx_mbox *mbox = chan->con_priv;
62 	reg = readl(mbox->base + RWTM_HOST_INT_RESET);
68 		dev_err(mbox->dev, "Secure processor command queue full\n");
70 	writel(reg, mbox->base + RWTM_HOST_INT_RESET);
79 	struct a37xx_mbox *mbox = chan->con_priv;
87 	reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS);
89 		dev_warn(mbox->dev, "Secure processor not ready\n");
92 		dev_err(mbox->dev, "Secure processor command queue full\n");
97 		writel(msg->args[i], mbox->base + RWTM_MBOX_PARAM(i));
98 	writel(msg->command, mbox->base + RWTM_MBOX_COMMAND);
105 	struct a37xx_mbox *mbox = chan->con_priv;
109 	ret = devm_request_irq(mbox->dev, mbox->irq, a37xx_mbox_irq_handler, 0,
112 		dev_err(mbox->dev, "Cannot request irq\n");
117 	reg = readl(mbox->base + RWTM_HOST_INT_MASK);
119 	writel(reg, mbox->base + RWTM_HOST_INT_MASK);
127 	struct a37xx_mbox *mbox = chan->con_priv;
130 	reg = readl(mbox->base + RWTM_HOST_INT_MASK);
132 	writel(reg, mbox->base + RWTM_HOST_INT_MASK);
134 	devm_free_irq(mbox->dev, mbox->irq, chan);
145 	struct a37xx_mbox *mbox;
149 	mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
150 	if (!mbox)
158 	mbox->base = devm_platform_ioremap_resource(pdev, 0);
159 	if (IS_ERR(mbox->base))
160 		return PTR_ERR(mbox->base);
162 	mbox->irq = platform_get_irq(pdev, 0);
163 	if (mbox->irq < 0)
164 		return mbox->irq;
166 	mbox->dev = &pdev->dev;
169 	chans[0].con_priv = mbox;
170 	mbox->controller.dev = mbox->dev;
171 	mbox->controller.num_chans = 1;
172 	mbox->controller.chans = chans;
173 	mbox->controller.ops = &a37xx_mbox_ops;
174 	mbox->controller.txdone_irq = true;
176 	ret = devm_mbox_controller_register(mbox->dev, &mbox->controller);
182 	platform_set_drvdata(pdev, mbox);