Lines Matching defs:hc
139 enable_hwirq(struct hfc_pci *hc)
141 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
142 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
146 disable_hwirq(struct hfc_pci *hc)
148 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
149 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
156 release_io_hfcpci(struct hfc_pci *hc)
159 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
160 del_timer(&hc->hw.timer);
161 dma_free_coherent(&hc->pdev->dev, 0x8000, hc->hw.fifos,
162 hc->hw.dmahandle);
163 iounmap(hc->hw.pci_io);
170 hfcpci_setmode(struct hfc_pci *hc)
172 if (hc->hw.protocol == ISDN_P_NT_S0) {
173 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
174 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
175 hc->hw.states = 1; /* G1 */
177 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
178 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
179 hc->hw.states = 2; /* F2 */
181 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
182 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
184 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
185 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
193 reset_hfcpci(struct hfc_pci *hc)
199 val = Read_hfc(hc, HFCPCI_CHIP_ID);
202 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
203 disable_hwirq(hc);
205 pci_write_config_word(hc->pdev, PCI_COMMAND,
207 val = Read_hfc(hc, HFCPCI_STATUS);
209 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
210 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
213 hc->hw.cirm = 0; /* Reset Off */
214 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
215 val = Read_hfc(hc, HFCPCI_STATUS);
220 val = Read_hfc(hc, HFCPCI_STATUS);
226 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
228 hc->hw.bswapped = 0; /* no exchange */
229 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
230 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
231 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
232 hc->hw.sctrl_r = 0;
233 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
234 hc->hw.mst_m = 0;
235 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
236 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
237 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
238 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
239 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
240 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
241 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
242 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
244 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
246 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
249 val = Read_hfc(hc, HFCPCI_INT_S1);
252 hfcpci_setmode(hc);
254 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
255 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
266 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
268 hc->hw.conn = 0x09;
270 hc->hw.conn = 0x36; /* set data flow directions */
271 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
272 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
273 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
274 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
275 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
277 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
278 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
279 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
280 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
283 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
284 val = Read_hfc(hc, HFCPCI_INT_S2);
293 struct hfc_pci *hc = from_timer(hc, t, hw.timer);
294 hc->hw.timer.expires = jiffies + 75;
297 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
298 * add_timer(&hc->hw.timer);
307 Sel_BCS(struct hfc_pci *hc, int channel)
309 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
310 (hc->bch[0].nr & channel))
311 return &hc->bch[0];
312 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
313 (hc->bch[1].nr & channel))
314 return &hc->bch[1];
323 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
329 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
330 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
332 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
333 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
336 hc->hw.fifo_en ^= fifo_state;
337 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
338 hc->hw.last_bfifo_cnt[fifo] = 0;
345 hc->hw.fifo_en |= fifo_state;
346 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
352 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
358 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
359 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
361 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
362 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
365 hc->hw.fifo_en ^= fifo_state;
366 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
367 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
379 hc->hw.fifo_en |= fifo_state;
380 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
381 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
452 receive_dmsg(struct hfc_pci *hc)
454 struct dchannel *dch = &hc->dch;
462 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
600 struct hfc_pci *hc = bch->hw;
607 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
608 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
609 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
610 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
613 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
614 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
615 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
639 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
641 hfcpci_clear_fifo_rx(hc, real_fifo);
643 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
662 hfcpci_fill_dfifo(struct hfc_pci *hc)
664 struct dchannel *dch = &hc->dch;
678 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
741 struct hfc_pci *hc = bch->hw;
759 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
760 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
761 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
763 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
764 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
940 struct hfc_pci *hc = dch->hw;
943 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
944 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
945 hc->hw.nt_timer = 0;
947 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
948 hc->hw.mst_m |= HFCPCI_MASTER;
949 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
957 struct hfc_pci *hc = dch->hw;
964 if (hc->hw.nt_timer < 0) {
965 hc->hw.nt_timer = 0;
968 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
969 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
971 (void) Read_hfc(hc, HFCPCI_INT_S1);
972 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
974 Write_hfc(hc, HFCPCI_STATES, 4);
976 } else if (hc->hw.nt_timer == 0) {
977 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
978 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
979 hc->hw.nt_timer = NT_T1_COUNT;
980 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
981 hc->hw.ctmt |= HFCPCI_TIM3_125;
982 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
987 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
989 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
993 hc->hw.nt_timer = 0;
996 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
997 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
999 hc->hw.mst_m &= ~HFCPCI_MASTER;
1000 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1006 hc->hw.nt_timer = 0;
1009 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1010 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1020 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1021 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1022 hc->hw.nt_timer = NT_T3_COUNT;
1023 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1024 hc->hw.ctmt |= HFCPCI_TIM3_125;
1025 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1035 struct hfc_pci *hc = dch->hw;
1037 if (hc->hw.protocol == ISDN_P_NT_S0) {
1039 hc->hw.nt_timer < 0)
1053 struct hfc_pci *hc = dch->hw;
1058 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1059 hc->hw.mst_m |= HFCPCI_MASTER;
1060 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1063 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1066 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1067 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1068 hc->hw.mst_m |= HFCPCI_MASTER;
1069 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1070 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1075 hc->hw.mst_m &= ~HFCPCI_MASTER;
1076 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1092 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1143 struct hfc_pci *hc = dev_id;
1148 spin_lock(&hc->lock);
1149 if (!(hc->hw.int_m2 & 0x08)) {
1150 spin_unlock(&hc->lock);
1153 stat = Read_hfc(hc, HFCPCI_STATUS);
1155 val = Read_hfc(hc, HFCPCI_INT_S1);
1156 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1161 spin_unlock(&hc->lock);
1164 hc->irqcnt++;
1166 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1168 val &= hc->hw.int_m1;
1170 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1171 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1173 hc->dch.state, exval);
1174 hc->dch.state = exval;
1175 schedule_event(&hc->dch, FLG_PHCHANGE);
1179 if (hc->hw.protocol == ISDN_P_NT_S0) {
1180 if ((--hc->hw.nt_timer) < 0)
1181 schedule_event(&hc->dch, FLG_PHCHANGE);
1184 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1187 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1190 else if (hc->dch.debug)
1194 bch = Sel_BCS(hc, 2);
1197 else if (hc->dch.debug)
1201 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1204 else if (hc->dch.debug)
1208 bch = Sel_BCS(hc, 2);
1211 else if (hc->dch.debug)
1215 receive_dmsg(hc);
1217 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1218 del_timer(&hc->dch.timer);
1219 tx_dirq(&hc->dch);
1221 spin_unlock(&hc->lock);
1239 struct hfc_pci *hc = bch->hw;
1251 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1258 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1261 if (hc->chanlimit > 1) {
1262 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1263 hc->hw.sctrl_e &= ~0x80;
1267 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1268 hc->hw.sctrl_e |= 0x80;
1270 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1271 hc->hw.sctrl_e &= ~0x80;
1275 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1276 hc->hw.sctrl_e &= ~0x80;
1288 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1289 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1291 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1292 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1295 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1296 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS |
1299 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1300 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS |
1305 hc->hw.cirm &= 0x7f;
1307 hc->hw.cirm &= 0xbf;
1317 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1318 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1320 hc->hw.sctrl |= SCTRL_B2_ENA;
1321 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1323 hc->hw.cirm |= 0x80;
1326 hc->hw.sctrl |= SCTRL_B1_ENA;
1327 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1329 hc->hw.cirm |= 0x40;
1333 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1335 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1337 hc->hw.ctmt |= 2;
1338 hc->hw.conn &= ~0x18;
1340 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1342 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1344 hc->hw.ctmt |= 1;
1345 hc->hw.conn &= ~0x03;
1352 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1353 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1355 hc->hw.sctrl |= SCTRL_B2_ENA;
1356 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1358 hc->hw.sctrl |= SCTRL_B1_ENA;
1359 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1362 hc->hw.last_bfifo_cnt[1] = 0;
1363 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1364 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1366 hc->hw.ctmt &= ~2;
1367 hc->hw.conn &= ~0x18;
1369 hc->hw.last_bfifo_cnt[0] = 0;
1370 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1371 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1373 hc->hw.ctmt &= ~1;
1374 hc->hw.conn &= ~0x03;
1382 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1388 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1397 hc->hw.conn &= 0xc7;
1398 hc->hw.conn |= 0x08;
1403 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1404 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1406 hc->hw.conn &= 0xf8;
1407 hc->hw.conn |= 0x01;
1412 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1413 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1416 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1417 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1418 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1419 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1420 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1421 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1422 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1424 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1432 struct hfc_pci *hc = bch->hw;
1447 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1449 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1450 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1452 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1453 hc->hw.ctmt |= 2;
1454 hc->hw.conn &= ~0x18;
1456 hc->hw.cirm |= 0x80;
1459 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1460 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1462 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1463 hc->hw.ctmt |= 1;
1464 hc->hw.conn &= ~0x03;
1466 hc->hw.cirm |= 0x40;
1472 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1474 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1475 hc->hw.last_bfifo_cnt[1] = 0;
1476 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1477 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1478 hc->hw.ctmt &= ~2;
1479 hc->hw.conn &= ~0x18;
1481 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1482 hc->hw.last_bfifo_cnt[0] = 0;
1483 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1484 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1485 hc->hw.ctmt &= ~1;
1486 hc->hw.conn &= ~0x03;
1493 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1494 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1495 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1496 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1497 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1499 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1507 struct hfc_pci *hc = bch->hw;
1510 spin_lock_irqsave(&hc->lock, flags);
1513 spin_unlock_irqrestore(&hc->lock, flags);
1528 struct hfc_pci *hc = bch->hw;
1536 spin_lock_irqsave(&hc->lock, flags);
1538 spin_unlock_irqrestore(&hc->lock, flags);
1541 spin_lock_irqsave(&hc->lock, flags);
1543 spin_unlock_irqrestore(&hc->lock, flags);
1546 spin_lock_irqsave(&hc->lock, flags);
1548 spin_unlock_irqrestore(&hc->lock, flags);
1577 struct hfc_pci *hc = dch->hw;
1585 spin_lock_irqsave(&hc->lock, flags);
1591 spin_unlock_irqrestore(&hc->lock, flags);
1594 spin_unlock_irqrestore(&hc->lock, flags);
1597 spin_lock_irqsave(&hc->lock, flags);
1598 if (hc->hw.protocol == ISDN_P_NT_S0) {
1600 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1601 hc->hw.mst_m |= HFCPCI_MASTER;
1602 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1604 spin_unlock_irqrestore(&hc->lock, flags);
1610 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1614 spin_unlock_irqrestore(&hc->lock, flags);
1618 spin_lock_irqsave(&hc->lock, flags);
1619 if (hc->hw.protocol == ISDN_P_NT_S0) {
1624 Write_hfc(hc, HFCPCI_STATES, 0x40);
1640 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1642 hc->hw.mst_m &= ~HFCPCI_MASTER;
1643 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1645 spin_unlock_irqrestore(&hc->lock, flags);
1649 spin_unlock_irqrestore(&hc->lock, flags);
1665 struct hfc_pci *hc = bch->hw;
1672 spin_lock_irqsave(&hc->lock, flags);
1678 spin_unlock_irqrestore(&hc->lock, flags);
1681 spin_lock_irqsave(&hc->lock, flags);
1686 spin_unlock_irqrestore(&hc->lock, flags);
1708 inithfcpci(struct hfc_pci *hc)
1711 timer_setup(&hc->dch.timer, hfcpci_dbusy_timer, 0);
1712 hc->chanlimit = 2;
1713 mode_hfcpci(&hc->bch[0], 1, -1);
1714 mode_hfcpci(&hc->bch[1], 2, -1);
1719 init_card(struct hfc_pci *hc)
1727 spin_lock_irqsave(&hc->lock, flags);
1728 disable_hwirq(hc);
1729 spin_unlock_irqrestore(&hc->lock, flags);
1730 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1732 "mISDN: couldn't get interrupt %d\n", hc->irq);
1735 spin_lock_irqsave(&hc->lock, flags);
1736 reset_hfcpci(hc);
1738 inithfcpci(hc);
1744 enable_hwirq(hc);
1745 spin_unlock_irqrestore(&hc->lock, flags);
1750 hc->irq, hc->irqcnt);
1752 spin_lock_irqsave(&hc->lock, flags);
1753 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1754 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1756 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1757 if (!hc->irqcnt) {
1760 "during init %d\n", hc->irq, 4 - cnt);
1764 reset_hfcpci(hc);
1768 spin_unlock_irqrestore(&hc->lock, flags);
1769 hc->initdone = 1;
1773 disable_hwirq(hc);
1774 spin_unlock_irqrestore(&hc->lock, flags);
1775 free_irq(hc->irq, hc);
1780 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1797 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1803 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1804 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1805 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1806 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1809 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1815 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1816 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1817 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1818 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1821 hc->hw.trm |= 0x80; /* enable IOM-loop */
1823 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1824 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1825 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1827 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1839 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1845 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1846 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1847 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1853 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1854 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1855 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1856 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1857 hc->hw.trm |= 0x80;
1858 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1861 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1862 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1863 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1866 ret = l1_event(hc->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
1878 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1885 hc->dch.dev.id, __builtin_return_address(0));
1892 if (!hc->initdone) {
1894 err = create_l1(&hc->dch, hfc_l1callback);
1898 hc->hw.protocol = rq->protocol;
1900 err = init_card(hc);
1905 if (hc->hw.protocol == ISDN_P_TE_S0)
1906 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1908 err = create_l1(&hc->dch, hfc_l1callback);
1912 hc->hw.protocol = rq->protocol;
1914 hfcpci_setmode(hc);
1918 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1919 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1930 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1938 bch = &hc->bch[rq->adr.channel - 1];
1956 struct hfc_pci *hc = dch->hw;
1968 err = open_dchannel(hc, ch, rq);
1970 err = open_bchannel(hc, rq);
1975 __func__, hc->dch.dev.id,
1980 err = channel_ctrl(hc, arg);
1992 setup_hw(struct hfc_pci *hc)
1997 hc->hw.cirm = 0;
1998 hc->dch.state = 0;
1999 pci_set_master(hc->pdev);
2000 if (!hc->irq) {
2004 hc->hw.pci_io =
2005 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2007 if (!hc->hw.pci_io) {
2013 if (dma_set_mask(&hc->pdev->dev, 0xFFFF8000)) {
2018 buffer = dma_alloc_coherent(&hc->pdev->dev, 0x8000, &hc->hw.dmahandle,
2026 hc->hw.fifos = buffer;
2027 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2028 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2029 if (unlikely(!hc->hw.pci_io)) {
2032 dma_free_coherent(&hc->pdev->dev, 0x8000, hc->hw.fifos,
2033 hc->hw.dmahandle);
2039 (u_long) hc->hw.pci_io, hc->hw.fifos,
2040 &hc->hw.dmahandle, hc->irq, HZ);
2043 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2044 hc->hw.int_m2 = 0;
2045 disable_hwirq(hc);
2046 hc->hw.int_m1 = 0;
2047 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2050 timer_setup(&hc->hw.timer, hfcpci_Timer, 0);
2052 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2057 release_card(struct hfc_pci *hc) {
2060 spin_lock_irqsave(&hc->lock, flags);
2061 hc->hw.int_m2 = 0; /* interrupt output off ! */
2062 disable_hwirq(hc);
2063 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2064 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2065 if (hc->dch.timer.function != NULL) {
2066 del_timer(&hc->dch.timer);
2067 hc->dch.timer.function = NULL;
2069 spin_unlock_irqrestore(&hc->lock, flags);
2070 if (hc->hw.protocol == ISDN_P_TE_S0)
2071 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2072 if (hc->initdone)
2073 free_irq(hc->irq, hc);
2074 release_io_hfcpci(hc); /* must release after free_irq! */
2075 mISDN_unregister_device(&hc->dch.dev);
2076 mISDN_freebchannel(&hc->bch[1]);
2077 mISDN_freebchannel(&hc->bch[0]);
2078 mISDN_freedchannel(&hc->dch);
2079 pci_set_drvdata(hc->pdev, NULL);
2080 kfree(hc);
2274 struct hfc_pci *hc = dev_get_drvdata(dev);
2276 if (hc == NULL)
2279 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2280 spin_lock_irq(&hc->lock);
2281 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2286 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2291 spin_unlock_irq(&hc->lock);