hardware/mISDN/avmfritz.c

129 	struct hdlc_hw		hdlc[2];
261 __write_ctrl_pci(struct fritzcard *fc, struct hdlc_hw *hdlc, u32 channel) {
265 	outl(hdlc->ctrl.ctrl, fc->addr + CHIP_WINDOW + HDLC_STATUS);
269 __write_ctrl_pciv2(struct fritzcard *fc, struct hdlc_hw *hdlc, u32 channel) {
270 	outl(hdlc->ctrl.ctrl, fc->addr + (channel == 2 ? AVM_HDLC_STATUS_2 :
277 	struct hdlc_hw *hdlc;
279 	hdlc = &fc->hdlc[(bch->nr - 1) & 1];
280 	pr_debug("%s: hdlc %c wr%x ctrl %x\n", fc->name, '@' + bch->nr,
281 		 which, hdlc->ctrl.ctrl);
284 		__write_ctrl_pciv2(fc, hdlc, bch->nr);
287 		__write_ctrl_pci(fc, hdlc, bch->nr);
339 	struct hdlc_hw *hdlc;
342 	hdlc = &fc->hdlc[(bch->nr - 1) & 1];
343 	pr_debug("%s: hdlc %c protocol %x-->%x ch %d\n", fc->name,
345 	hdlc->ctrl.ctrl = 0;
355 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
356 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS;
364 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
365 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS;
367 		hdlc->ctrl.sr.cmd = HDLC_CMD_XRS;
369 		hdlc->ctrl.sr.cmd = 0;
374 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;
375 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_ITF_FLG;
377 		hdlc->ctrl.sr.cmd = HDLC_CMD_XRS;
379 		hdlc->ctrl.sr.cmd = 0;
439 	struct hdlc_hw *hdlc;
446 	hdlc = &fc->hdlc[idx];
461 	hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XME;
466 			hdlc->ctrl.sr.cmd |= HDLC_CMD_XME;
476 	hdlc->ctrl.sr.xml = ((count == fs) ? 0 : count);
478 		__write_ctrl_pciv2(fc, hdlc, bch->nr);
482 		__write_ctrl_pci(fc, hdlc, bch->nr);
528 	struct hdlc_hw	*hdlc;
530 	hdlc = &fc->hdlc[(bch->nr - 1) & 1];
543 			hdlc->ctrl.sr.xml = 0;
544 			hdlc->ctrl.sr.cmd |= HDLC_CMD_RRS;
546 			hdlc->ctrl.sr.cmd &= ~HDLC_CMD_RRS;
585 		hdlc->ctrl.sr.xml = 0;
586 		hdlc->ctrl.sr.cmd |= HDLC_CMD_XRS;
588 		hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XRS;