drivers/irqchip/irq-xilinx-intc.c

48 static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
51 		iowrite32be(data, irqc->base + reg);
53 		iowrite32(data, irqc->base + reg);
56 static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
59 		return ioread32be(irqc->base + reg);
61 		return ioread32(irqc->base + reg);
66 	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
76 		xintc_write(irqc, IAR, mask);
78 	xintc_write(irqc, SIE, mask);
83 	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
86 	xintc_write(irqc, CIE, BIT(d->hwirq));
91 	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
94 	xintc_write(irqc, IAR, BIT(d->hwirq));
99 	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
103 	xintc_write(irqc, CIE, mask);
104 	xintc_write(irqc, IAR, mask);
117 	struct xintc_irq_chip *irqc = d->host_data;
119 	if (irqc->intr_mask & BIT(hw)) {
128 	irq_set_chip_data(irq, irqc);
140 	struct xintc_irq_chip *irqc;
142 	irqc = irq_data_get_irq_handler_data(&desc->irq_data);
145 		u32 hwirq = xintc_read(irqc, IVR);
150 		generic_handle_domain_irq(irqc->root_domain, hwirq);
171 	struct xintc_irq_chip *irqc;
174 	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
175 	if (!irqc)
177 	irqc->base = of_iomap(intc, 0);
178 	BUG_ON(!irqc->base);
180 	ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
186 	ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
189 		irqc->intr_mask = 0;
192 	if (irqc->intr_mask >> irqc->nr_irq)
196 		intc, irqc->nr_irq, irqc->intr_mask);
203 	xintc_write(irqc, IER, 0);
206 	xintc_write(irqc, IAR, 0xffffffff);
209 	xintc_write(irqc, MER, MER_HIE | MER_ME);
210 	if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
212 		xintc_write(irqc, MER, MER_HIE | MER_ME);
215 	irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
216 						  &xintc_irq_domain_ops, irqc);
217 	if (!irqc->root_domain) {
228 							 irqc);
235 		primary_intc = irqc;
243 	iounmap(irqc->base);
244 	kfree(irqc);