drivers/irqchip/irq-vic.c

50  * @base: The register base for the VIC.
51  * @irq: The IRQ number for the base of the VIC.
62 	void __iomem	*base;
83  * @base: Base of the VIC.
88 static void vic_init2(void __iomem *base)
93 		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
97 	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
103 	void __iomem *base = vic->base;
105 	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
108 	vic_init2(base);
110 	writel(vic->int_select, base + VIC_INT_SELECT);
111 	writel(vic->protect, base + VIC_PROTECT);
114 	writel(vic->int_enable, base + VIC_INT_ENABLE);
115 	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
119 	writel(vic->soft_int, base + VIC_INT_SOFT);
120 	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
133 	void __iomem *base = vic->base;
135 	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
137 	vic->int_select = readl(base + VIC_INT_SELECT);
138 	vic->int_enable = readl(base + VIC_INT_ENABLE);
139 	vic->soft_int = readl(base + VIC_INT_SOFT);
140 	vic->protect = readl(base + VIC_PROTECT);
145 	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
146 	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
192 	irq_set_chip_data(irq, v->base);
208 	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
225 	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
254  * @base: The base address of the VIC.
256  * @irq: The base IRQ for the VIC.
267 static void __init vic_register(void __iomem *base, unsigned int parent_irq,
281 	v->base = base;
298 	/* If no base IRQ was passed, figure out our allocated base */
307 	void __iomem *base = irq_data_get_irq_chip_data(d);
309 	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
311 	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
316 	void __iomem *base = irq_data_get_irq_chip_data(d);
318 	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
323 	void __iomem *base = irq_data_get_irq_chip_data(d);
325 	writel(1 << irq, base + VIC_INT_ENABLE);
374 static void __init vic_disable(void __iomem *base)
376 	writel(0, base + VIC_INT_SELECT);
377 	writel(0, base + VIC_INT_ENABLE);
378 	writel(~0, base + VIC_INT_ENABLE_CLEAR);
379 	writel(0, base + VIC_ITCR);
380 	writel(~0, base + VIC_INT_SOFT_CLEAR);
383 static void __init vic_clear_interrupts(void __iomem *base)
387 	writel(0, base + VIC_PL190_VECT_ADDR);
391 		value = readl(base + VIC_PL190_VECT_ADDR);
392 		writel(value, base + VIC_PL190_VECT_ADDR);
400  * the probe function is called twice, with base set to offset 000
403 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
407 	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
410 	vic_disable(base);
416 	 * the second base address, which is 0x20 in the page
419 		vic_clear_interrupts(base);
423 			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
427 		writel(32, base + VIC_PL190_DEF_VECT_ADDR);
430 	vic_register(base, 0, irq_start, vic_sources, 0, node);
433 static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,
444 		addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
449 	       base, cellid, vendor);
453 		vic_init_st(base, irq_start, vic_sources, node);
463 	vic_disable(base);
466 	vic_clear_interrupts(base);
468 	vic_init2(base);
470 	vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);
475  * @base: iomem base address
480 void __init vic_init(void __iomem *base, unsigned int irq_start,
483 	__vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);