drivers/irqchip/irq-tb10x.c

30 static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
33 	irq_reg_writel(gc, val, reg);
36 static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
38 	return irq_reg_readl(gc, reg);
43 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
48 	irq_gc_lock(gc);
50 	mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
51 	pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;
70 		irq_gc_unlock(gc);
79 	ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
80 	ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
81 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
83 	irq_gc_unlock(gc);
101 	struct irq_chip_generic *gc;
143 	gc = domain->gc->gc[0];
144 	gc->reg_base                         = reg_base;
146 	gc->chip_types[0].type               = IRQ_TYPE_LEVEL_MASK;
147 	gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
148 	gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
149 	gc->chip_types[0].chip.irq_set_type  = tb10x_irq_set_type;
150 	gc->chip_types[0].regs.mask          = AB_IRQCTL_INT_ENABLE;
152 	gc->chip_types[1].type               = IRQ_TYPE_EDGE_BOTH;
153 	gc->chip_types[1].chip.name          = gc->chip_types[0].chip.name;
154 	gc->chip_types[1].chip.irq_ack       = irq_gc_ack_set_bit;
155 	gc->chip_types[1].chip.irq_mask      = irq_gc_mask_clr_bit;
156 	gc->chip_types[1].chip.irq_unmask    = irq_gc_mask_set_bit;
157 	gc->chip_types[1].chip.irq_set_type  = tb10x_irq_set_type;
158 	gc->chip_types[1].regs.ack           = AB_IRQCTL_INT_STATUS;
159 	gc->chip_types[1].regs.mask          = AB_IRQCTL_INT_ENABLE;
160 	gc->chip_types[1].handler            = handle_edge_irq;
169 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
170 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
171 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
172 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);