Lines Matching refs:gc
35 struct irq_domain_chip_generic *dgc = orion_irq_domain->gc;
39 struct irq_chip_generic *gc =
41 u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) &
42 gc->mask_cache;
46 gc->irq_base + hwirq);
73 panic("%pOFn: unable to alloc irq domain gc\n", np);
76 struct irq_chip_generic *gc =
85 gc->reg_base = ioremap(r.start, resource_size(&r));
86 if (!gc->reg_base)
89 gc->chip_types[0].regs.mask = ORION_IRQ_MASK;
90 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
91 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
94 writel(0, gc->reg_base + ORION_IRQ_MASK);
112 struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
113 u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &
114 gc->mask_cache;
119 generic_handle_domain_irq(d, gc->irq_base + hwirq);
143 struct irq_chip_generic *gc;
159 pr_err("%pOFn: unable to alloc irq domain gc\n", np);
181 gc = irq_get_domain_generic_chip(domain, 0);
182 gc->reg_base = ioremap(r.start, resource_size(&r));
183 if (!gc->reg_base) {
188 gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;
189 gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;
190 gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup;
191 gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
192 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
193 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
196 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
197 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);