drivers/irqchip/irq-mvebu-pic.c

36 static void mvebu_pic_reset(struct mvebu_pic *pic)
39 	writel(0, pic->base + PIC_MASK);
40 	writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE);
45 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
47 	writel(1 << d->hwirq, pic->base + PIC_CAUSE);
52 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
55 	reg =  readl(pic->base + PIC_MASK);
57 	writel(reg, pic->base + PIC_MASK);
62 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
65 	reg = readl(pic->base + PIC_MASK);
67 	writel(reg, pic->base + PIC_MASK);
72 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
74 	seq_printf(p, dev_name(&pic->pdev->dev));
87 	struct mvebu_pic *pic = domain->host_data;
90 	irq_set_chip_data(virq, pic);
105 	struct mvebu_pic *pic = irq_desc_get_handler_data(desc);
109 	irqmap = readl_relaxed(pic->base + PIC_CAUSE);
113 		generic_handle_domain_irq(pic->domain, irqn);
120 	struct mvebu_pic *pic = data;
122 	mvebu_pic_reset(pic);
123 	enable_percpu_irq(pic->parent_irq, IRQ_TYPE_NONE);
128 	struct mvebu_pic *pic = data;
130 	disable_percpu_irq(pic->parent_irq);
136 	struct mvebu_pic *pic;
138 	pic = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pic), GFP_KERNEL);
139 	if (!pic)
142 	pic->pdev = pdev;
143 	pic->base = devm_platform_ioremap_resource(pdev, 0);
144 	if (IS_ERR(pic->base))
145 		return PTR_ERR(pic->base);
147 	pic->parent_irq = irq_of_parse_and_map(node, 0);
148 	if (pic->parent_irq <= 0) {
153 	pic->domain = irq_domain_add_linear(node, PIC_MAX_IRQS,
154 					    &mvebu_pic_domain_ops, pic);
155 	if (!pic->domain) {
160 	irq_set_chained_handler(pic->parent_irq, mvebu_pic_handle_cascade_irq);
161 	irq_set_handler_data(pic->parent_irq, pic);
163 	on_each_cpu(mvebu_pic_enable_percpu_irq, pic, 1);
165 	platform_set_drvdata(pdev, pic);
172 	struct mvebu_pic *pic = platform_get_drvdata(pdev);
174 	on_each_cpu(mvebu_pic_disable_percpu_irq, pic, 1);
175 	irq_domain_remove(pic->domain);
179 	{ .compatible = "marvell,armada-8k-pic", },
188 		.name		= "mvebu-pic",