drivers/irqchip/irq-atmel-aic.c

63 	struct irq_domain_chip_generic *dgc = aic_domain->gc;
64 	struct irq_chip_generic *gc = dgc->gc[0];
68 	irqnr = irq_reg_readl(gc, AT91_AIC_IVR);
69 	irqstat = irq_reg_readl(gc, AT91_AIC_ISR);
72 		irq_reg_writel(gc, 0, AT91_AIC_EOICR);
79 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
82 	irq_gc_lock(gc);
83 	irq_reg_writel(gc, d->mask, AT91_AIC_ISCR);
84 	irq_gc_unlock(gc);
91 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
95 	smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq));
100 	irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq));
108 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
110 	irq_gc_lock(gc);
111 	irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);
112 	irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR);
113 	irq_gc_unlock(gc);
118 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
120 	irq_gc_lock(gc);
121 	irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR);
122 	irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);
123 	irq_gc_unlock(gc);
128 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
130 	irq_gc_lock(gc);
131 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
132 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
133 	irq_gc_unlock(gc);
143 	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
151 		irq_reg_writel(gc, 0, AT91_AIC_EOICR);
158 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);
161 	irq_reg_writel(gc, 0, AT91_AIC_DCR);
164 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
165 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
168 		irq_reg_writel(gc, i, AT91_AIC_SVR(i));
177 	struct irq_domain_chip_generic *dgc = d->gc;
178 	struct irq_chip_generic *gc;
196 	gc = dgc->gc[idx];
198 	irq_gc_lock_irqsave(gc, flags);
199 	smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq));
201 	irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));
202 	irq_gc_unlock_irqrestore(gc, flags);
244 	struct irq_chip_generic *gc;
256 	gc = irq_get_domain_generic_chip(domain, 0);
258 	gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
259 	gc->chip_types[0].regs.enable = AT91_AIC_IECR;
260 	gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
261 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
262 	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
263 	gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
264 	gc->chip_types[0].chip.irq_set_type = aic_set_type;
265 	gc->chip_types[0].chip.irq_suspend = aic_suspend;
266 	gc->chip_types[0].chip.irq_resume = aic_resume;
267 	gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;