Lines Matching refs:vic

7  *  Based on irq-vic.c:
58 static void vic_init_hw(struct aspeed_vic *vic)
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);
71 writel(0, vic->base + AVIC_INT_SELECT);
72 writel(0, vic->base + AVIC_INT_SELECT + 4);
78 sense = readl(vic->base + AVIC_INT_SENSE);
79 vic->edge_sources[0] = ~sense;
80 sense = readl(vic->base + AVIC_INT_SENSE + 4);
81 vic->edge_sources[1] = ~sense;
84 writel(0xffffffff, vic->base + AVIC_EDGE_CLR);
85 writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);
90 struct aspeed_vic *vic = system_avic;
95 stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);
97 stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);
103 generic_handle_domain_irq(vic->dom, irq);
109 struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
114 if (vic->edge_sources[sidx] & sbit)
115 writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
120 struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
124 writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
129 struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
133 writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);
139 struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
144 writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
147 if (vic->edge_sources[sidx] & sbit)
148 writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
162 struct aspeed_vic *vic = d->host_data;
170 if (vic->edge_sources[sidx] & sbit)
174 irq_set_chip_data(irq, vic);
188 struct aspeed_vic *vic;
199 vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL);
200 if (WARN_ON(!vic)) {
204 vic->base = regs;
207 vic_init_hw(vic);
210 system_avic = vic;
214 vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0,
215 &avic_dom_ops, vic);
220 IRQCHIP_DECLARE(ast2400_vic, "aspeed,ast2400-vic", avic_of_init);
221 IRQCHIP_DECLARE(ast2500_vic, "aspeed,ast2500-vic", avic_of_init);