iommu/intel/svm.c

22 #include "iommu.h"
25 #include "../iommu-pages.h"
30 int intel_svm_enable_prq(struct intel_iommu *iommu)
35 	iommu->prq = iommu_alloc_pages_node(iommu->node, GFP_KERNEL, PRQ_ORDER);
36 	if (!iommu->prq) {
38 			iommu->name);
42 	irq = dmar_alloc_hwirq(IOMMU_IRQ_ID_OFFSET_PRQ + iommu->seq_id, iommu->node, iommu);
45 		       iommu->name);
49 	iommu->pr_irq = irq;
51 	snprintf(iommu->iopfq_name, sizeof(iommu->iopfq_name),
52 		 "dmar%d-iopfq", iommu->seq_id);
53 	iopfq = iopf_queue_alloc(iommu->iopfq_name);
55 		pr_err("IOMMU: %s: Failed to allocate iopf queue\n", iommu->name);
59 	iommu->iopf_queue = iopfq;
61 	snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
64 				   iommu->prq_name, iommu);
67 		       iommu->name);
70 	dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
71 	dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
72 	dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
74 	init_completion(&iommu->prq_complete);
79 	iopf_queue_free(iommu->iopf_queue);
80 	iommu->iopf_queue = NULL;
83 	iommu->pr_irq = 0;
85 	iommu_free_pages(iommu->prq, PRQ_ORDER);
86 	iommu->prq = NULL;
91 int intel_svm_finish_prq(struct intel_iommu *iommu)
93 	dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
94 	dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
95 	dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
97 	if (iommu->pr_irq) {
98 		free_irq(iommu->pr_irq, iommu);
99 		dmar_free_hwirq(iommu->pr_irq);
100 		iommu->pr_irq = 0;
103 	if (iommu->iopf_queue) {
104 		iopf_queue_free(iommu->iopf_queue);
105 		iommu->iopf_queue = NULL;
108 	iommu_free_pages(iommu->prq, PRQ_ORDER);
109 	iommu->prq = NULL;
114 void intel_svm_check(struct intel_iommu *iommu)
116 	if (!pasid_supported(iommu))
120 	    !cap_fl1gp_support(iommu->cap)) {
122 		       iommu->name);
127 	    !cap_fl5lp_support(iommu->cap)) {
129 		       iommu->name);
133 	iommu->flags |= VTD_FLAG_SVM_CAPABLE;
178 		intel_pasid_tear_down_entry(info->iommu, dev_pasid->dev,
201 	struct intel_iommu *iommu = info->iommu;
221 	ret = intel_pasid_setup_first_level(iommu, dev, mm->pgd, pasid,
296 	struct intel_iommu *iommu;
310 	iommu = info->iommu;
314 	did = domain_id_iommu(domain, iommu);
322 	reinit_completion(&iommu->prq_complete);
323 	tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
324 	head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
328 		req = &iommu->prq[head / sizeof(*req)];
334 		wait_for_completion(&iommu->prq_complete);
358 	reinit_completion(&iommu->prq_complete);
359 	qi_submit_sync(iommu, desc, 3, QI_OPT_WAIT_DRAIN);
360 	if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) {
361 		wait_for_completion(&iommu->prq_complete);
382 static void intel_svm_prq_report(struct intel_iommu *iommu, struct device *dev,
404 static void handle_bad_prq_event(struct intel_iommu *iommu,
410 	       iommu->name, ((unsigned long long *)req)[0],
424 	qi_submit_sync(iommu, &desc, 1, 0);
429 	struct intel_iommu *iommu = d;
439 	writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
441 	tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
442 	head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
445 		req = &iommu->prq[head / sizeof(*req)];
450 			       iommu->name);
452 			handle_bad_prq_event(iommu, req, QI_RESP_INVALID);
458 			       iommu->name);
464 			       iommu->name);
470 			       iommu->name);
479 		 * If prq is to be handled outside iommu driver via receiver of
482 		mutex_lock(&iommu->iopf_lock);
483 		dev = device_rbtree_find(iommu, req->rid);
485 			mutex_unlock(&iommu->iopf_lock);
489 		intel_svm_prq_report(iommu, dev, req);
490 		trace_prq_report(iommu, dev, req->qw_0, req->qw_1,
492 				 iommu->prq_seq_number++);
493 		mutex_unlock(&iommu->iopf_lock);
498 	dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
504 	if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) {
506 				    iommu->name);
507 		head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
508 		tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
510 			iopf_queue_discard_partial(iommu->iopf_queue);
511 			writel(DMA_PRS_PRO, iommu->reg + DMAR_PRS_REG);
513 					    iommu->name);
517 	if (!completion_done(&iommu->prq_complete))
518 		complete(&iommu->prq_complete);
527 	struct intel_iommu *iommu = info->iommu;
548 	qi_submit_sync(iommu, &desc, 1, 0);