Lines Matching defs:hwc
300 struct hw_perf_event *hwc = &event->hw;
315 hwc->config = iommu_event_config(event);
323 struct hw_perf_event *hwc = &event->hw;
328 prev_count = local64_read(&hwc->prev_count);
329 new_count = dmar_readq(iommu_event_base(iommu_pmu, hwc->idx));
330 if (local64_xchg(&hwc->prev_count, new_count) != prev_count)
347 struct hw_perf_event *hwc = &event->hw;
350 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
353 if (WARN_ON_ONCE(hwc->idx < 0 || hwc->idx >= IOMMU_PMU_IDX_MAX))
359 hwc->state = 0;
362 count = dmar_readq(iommu_event_base(iommu_pmu, hwc->idx));
363 local64_set((&hwc->prev_count), count);
375 ecmd_submit_sync(iommu, DMA_ECMD_ENABLE, hwc->idx, 0);
384 struct hw_perf_event *hwc = &event->hw;
386 if (!(hwc->state & PERF_HES_STOPPED)) {
387 ecmd_submit_sync(iommu, DMA_ECMD_DISABLE, hwc->idx, 0);
391 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
411 struct hw_perf_event *hwc = &event->hw;
430 hwc->idx = idx;
433 dmar_writeq(iommu_config_base(iommu_pmu, idx), hwc->config);
457 struct hw_perf_event *hwc = &event->hw;
464 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;