arm/arm-smmu/arm-smmu-qcom-debug.c

106 	struct qcom_tbu *tbu;
114 	list_for_each_entry(tbu, &tbu_list, list) {
115 		start = tbu->sid_range[0];
116 		end = start + tbu->sid_range[1];
118 		if (qsmmu->smmu.dev->of_node == tbu->smmu_np &&
120 			return tbu;
127 static int qcom_tbu_halt(struct qcom_tbu *tbu, struct arm_smmu_domain *smmu_domain)
133 	guard(spinlock_irqsave)(&tbu->halt_lock);
134 	if (tbu->halt_count) {
135 		tbu->halt_count++;
139 	val = readl_relaxed(tbu->base + DEBUG_SID_HALT_REG);
141 	writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
161 	if (readl_poll_timeout_atomic(tbu->base + DEBUG_SR_HALT_ACK_REG, status,
164 		dev_err(tbu->dev, "Timeout while trying to halt TBU!\n");
167 		val = readl_relaxed(tbu->base + DEBUG_SID_HALT_REG);
169 		writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
174 	tbu->halt_count = 1;
179 static void qcom_tbu_resume(struct qcom_tbu *tbu)
183 	guard(spinlock_irqsave)(&tbu->halt_lock);
184 	if (!tbu->halt_count) {
185 		WARN(1, "%s: halt_count is 0", dev_name(tbu->dev));
189 	if (tbu->halt_count > 1) {
190 		tbu->halt_count--;
194 	val = readl_relaxed(tbu->base + DEBUG_SID_HALT_REG);
196 	writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
198 	tbu->halt_count = 0;
202 					 struct qcom_tbu *tbu, dma_addr_t iova, u32 sid)
210 	val = readq_relaxed(tbu->base + DEBUG_SID_HALT_REG);
213 	writeq_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
214 	writeq_relaxed(iova, tbu->base + DEBUG_VA_ADDR_REG);
216 	writeq_relaxed(val, tbu->base + DEBUG_AXUSER_REG);
228 	writeq_relaxed(val, tbu->base + DEBUG_TXN_TRIGG_REG);
232 		val = readl_relaxed(tbu->base + DEBUG_SR_HALT_ACK_REG);
235 		val = readl_relaxed(tbu->base + DEBUG_PAR_REG);
244 	val = readq_relaxed(tbu->base + DEBUG_PAR_REG);
246 		dev_err(tbu->dev, "ATOS generated a fault interrupt! PAR = %llx, SID=0x%x\n",
249 		dev_err_ratelimited(tbu->dev, "ATOS translation timed out!\n");
254 	writeq_relaxed(0, tbu->base + DEBUG_TXN_TRIGG_REG);
255 	writeq_relaxed(0, tbu->base + DEBUG_VA_ADDR_REG);
256 	val = readl_relaxed(tbu->base + DEBUG_SID_HALT_REG);
258 	writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
269 	struct qcom_tbu *tbu;
276 	tbu = qcom_find_tbu(qsmmu, sid);
277 	if (!tbu)
280 	ret = icc_set_bw(tbu->path, 0, UINT_MAX);
284 	ret = clk_prepare_enable(tbu->clk);
288 	ret = qcom_tbu_halt(tbu, smmu_domain);
320 			phys = qcom_tbu_trigger_atos(smmu_domain, tbu, iova, sid);
335 	qcom_tbu_resume(tbu);
338 	readl_relaxed(tbu->base + DEBUG_SR_HALT_ACK_REG);
341 	clk_disable_unprepare(tbu->clk);
343 	icc_set_bw(tbu->path, 0, 0);
496 	struct qcom_tbu *tbu;
498 	tbu = devm_kzalloc(dev, sizeof(*tbu), GFP_KERNEL);
499 	if (!tbu)
502 	tbu->dev = dev;
503 	INIT_LIST_HEAD(&tbu->list);
504 	spin_lock_init(&tbu->halt_lock);
511 	tbu->smmu_np =  args.np;
512 	tbu->sid_range[0] = args.args[0];
513 	tbu->sid_range[1] = args.args[1];
516 	tbu->base = devm_of_iomap(dev, np, 0, NULL);
517 	if (IS_ERR(tbu->base))
518 		return PTR_ERR(tbu->base);
520 	tbu->clk = devm_clk_get_optional(dev, NULL);
521 	if (IS_ERR(tbu->clk))
522 		return PTR_ERR(tbu->clk);
524 	tbu->path = devm_of_icc_get(dev, NULL);
525 	if (IS_ERR(tbu->path))
526 		return PTR_ERR(tbu->path);
529 	list_add_tail(&tbu->list, &tbu_list);
535 	{ .compatible = "qcom,sc7280-tbu" },
536 	{ .compatible = "qcom,sdm845-tbu" },