iommu/amd/iommu.c

730 	u32 pasid;
735 	pasid   = (event[0] & EVENT_DOMID_MASK_HI) |
751 		amd_iommu_report_page_fault(iommu, devid, pasid, address, flags);
757 		dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
759 			pasid, address, flags);
769 		dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
771 			pasid, address, flags);
787 		dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
789 			pasid, address, flags);
798 		pasid = PPR_PASID(*((u64 *)__evt));
800 		dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
802 			pasid, address, flags, tag);
1090 				  ioasid_t pasid, bool gn)
1102 		cmd->data[0] |= pasid;
1110 				  ioasid_t pasid, bool gn)
1122 		cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1123 		cmd->data[1] |= (pasid & 0xff) << 16;
1130 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1137 		cmd->data[1]  = pasid;
1348 			      size_t size, ioasid_t pasid, bool gn)
1355 			      size, pasid, gn);
1458 	ioasid_t pasid = IOMMU_NO_PASID;
1473 		ret |= device_flush_iotlb(dev_data, address, size, pasid, gn);
1537 				     ioasid_t pasid, u64 address, size_t size)
1543 			      dev_data->gcr3_info.domid, pasid, true);
1547 		device_flush_iotlb(dev_data, address, size, pasid, true);
1553 				   ioasid_t pasid)
1556 					CMD_INV_IOMMU_ALL_PAGES_ADDRESS, pasid);
1627 int amd_iommu_complete_ppr(struct device *dev, u32 pasid, int status, int tag)
1636 	build_complete_ppr(&cmd, dev_data->devid, pasid, status,
1770 			   ioasid_t pasid, bool alloc)
1779 		index = (pasid >> (9 * level)) & 0x1ff;
1805 		       ioasid_t pasid, unsigned long gcr3, bool set)
1810 	pte = __get_gcr3_pte(gcr3_info, pasid, true);
1819 	amd_iommu_dev_flush_pasid_all(dev_data, pasid);
1823 int amd_iommu_set_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid,
1831 	ret = update_gcr3(dev_data, pasid, gcr3, true);
1839 int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid)
1846 	ret = update_gcr3(dev_data, pasid, 0, false);