hw/qib/qib_iba6120.c

359 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
753 	hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
968 	sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
969 	sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
1062 		u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1130 	extsval = qib_read_kreg64(dd, kr_extstatus);
1156 	dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1265 	val = qib_read_kreg64(dd, kr_serdes_cfg0);
1266 	config1 = qib_read_kreg64(dd, kr_serdes_cfg1);
1282 	qib_read_kreg64(dd, kr_scratch);
1302 	(void) qib_read_kreg64(dd, kr_scratch);
1314 	(void) qib_read_kreg64(dd, kr_scratch);
1316 	val = qib_read_kreg64(dd, kr_xgxs_cfg);
1328 	val = qib_read_kreg64(dd, kr_serdes_cfg0);
1346 	hwstat = qib_read_kreg64(dd, kr_hwerrstatus);
1382 		diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1405 	val = qib_read_kreg64(dd, kr_serdes_cfg0);
1452 		val = qib_read_kreg64(dd, kr_ibcstatus);
1523 		estat = qib_read_kreg64(dd, kr_errstatus);
2583 	errormask = qib_read_kreg64(dd, kr_errmask);
2589 	hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2665 	prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
3061 	read_val = qib_read_kreg64(dd, kr_extstatus);
3082 	dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3087 	val = qib_read_kreg64(dd, kr_sendpiosize);
3096 	val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3152 	val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3305 	qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3313 	qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3514 	if (qib_read_kreg64(dd, kr_hwerrstatus) &