hw/mlx5/devx.c

38 	/* must be last field in this structure */
43 	struct list_head list; /* headed in ev_file->event_list */
60 	struct list_head file_list; /* headed in ev_file->
63 	struct list_head xa_list; /* headed in devx_event->unaffiliated_list or
66 	struct list_head obj_list; /* headed in devx_object */
67 	struct list_head event_list; /* headed in ev_file->event_list or in
101 	void				*in;
114 	u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {};
125 	uctx = MLX5_ADDR_OF(create_uctx_in, in, uctx);
134 	MLX5_SET(create_uctx_in, in, opcode, MLX5_CMD_OP_CREATE_UCTX);
137 	err = mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
147 	u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {};
150 	MLX5_SET(destroy_uctx_in, in, opcode, MLX5_CMD_OP_DESTROY_UCTX);
151 	MLX5_SET(destroy_uctx_in, in, uid, uid);
153 	mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
282  * As the obj_id in the firmware is not globally unique the object type
291 static u32 devx_get_created_obj_id(const void *in, const void *out, u16 opcode)
326 		return MLX5_GET(set_fte_in, in, flow_index);
339 		return MLX5_GET(add_vxlan_udp_dport_in, in, vxlan_udp_port);
341 		return MLX5_GET(set_l2_table_entry_in, in, table_index);
353 		return MLX5_GET(attach_to_mcg_in, in, qpn);
365 static u64 devx_get_obj_id(const void *in)
367 	u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
374 					MLX5_GET(general_obj_in_cmd_hdr, in,
376 					MLX5_GET(general_obj_in_cmd_hdr, in,
381 					MLX5_GET(query_mkey_in, in,
386 					MLX5_GET(query_cq_in, in, cqn));
390 					MLX5_GET(modify_cq_in, in, cqn));
394 					MLX5_GET(query_sq_in, in, sqn));
398 					MLX5_GET(modify_sq_in, in, sqn));
402 					MLX5_GET(query_rq_in, in, rqn));
406 					MLX5_GET(modify_rq_in, in, rqn));
410 					MLX5_GET(query_rmp_in, in, rmpn));
414 					MLX5_GET(modify_rmp_in, in, rmpn));
418 					MLX5_GET(query_rqt_in, in, rqtn));
422 					MLX5_GET(modify_rqt_in, in, rqtn));
426 					MLX5_GET(query_tir_in, in, tirn));
430 					MLX5_GET(modify_tir_in, in, tirn));
434 					MLX5_GET(query_tis_in, in, tisn));
438 					MLX5_GET(modify_tis_in, in, tisn));
442 					MLX5_GET(query_flow_table_in, in,
447 					MLX5_GET(modify_flow_table_in, in,
452 					MLX5_GET(query_flow_group_in, in,
457 					MLX5_GET(query_fte_in, in,
462 					MLX5_GET(set_fte_in, in, flow_index));
466 					MLX5_GET(query_q_counter_in, in,
471 					MLX5_GET(query_flow_counter_in, in,
477 						 in, modify_header_id));
482 						 in, scheduling_element_id));
487 						 in, scheduling_element_id));
491 					MLX5_GET(add_vxlan_udp_dport_in, in,
496 					MLX5_GET(query_l2_table_entry_in, in,
501 					MLX5_GET(set_l2_table_entry_in, in,
506 					MLX5_GET(query_qp_in, in, qpn));
510 					MLX5_GET(rst2init_qp_in, in, qpn));
514 					MLX5_GET(init2init_qp_in, in, qpn));
518 					MLX5_GET(init2rtr_qp_in, in, qpn));
522 					MLX5_GET(rtr2rts_qp_in, in, qpn));
526 					MLX5_GET(rts2rts_qp_in, in, qpn));
530 					MLX5_GET(sqerr2rts_qp_in, in, qpn));
534 					MLX5_GET(qp_2err_in, in, qpn));
538 					MLX5_GET(qp_2rst_in, in, qpn));
542 					MLX5_GET(query_dct_in, in, dctn));
548 					MLX5_GET(query_xrq_in, in, xrqn));
552 					MLX5_GET(query_xrc_srq_in, in,
557 					MLX5_GET(arm_xrc_srq_in, in, xrc_srqn));
561 					MLX5_GET(query_srq_in, in, srqn));
565 					MLX5_GET(arm_rq_in, in, srq_number));
569 					MLX5_GET(drain_dct_in, in, dctn));
576 					MLX5_GET(arm_xrq_in, in, xrqn));
582 					  in, packet_reformat_id));
592 				 struct ib_uobject *uobj, const void *in)
595 	u64 obj_id = devx_get_obj_id(in);
670 		u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
690 static void devx_set_umem_valid(const void *in)
692 	u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
696 		MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1);
702 		MLX5_SET(create_cq_in, in, cq_umem_valid, 1);
703 		cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
711 		qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
713 		MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
721 		rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
732 		sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
740 		MLX5_SET(modify_cq_in, in, cq_umem_valid, 1);
747 		rmpc = MLX5_ADDR_OF(create_rmp_in, in, ctx);
758 		xrqc = MLX5_ADDR_OF(create_xrq_in, in, xrq_context);
769 		MLX5_SET(create_xrc_srq_in, in, xrc_srq_umem_valid, 1);
770 		xrc_srqc = MLX5_ADDR_OF(create_xrc_srq_in, in,
781 static bool devx_is_obj_create_cmd(const void *in, u16 *opcode)
783 	*opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
816 		u16 op_mod = MLX5_GET(set_fte_in, in, op_mod);
823 		u8 num_psv = MLX5_GET(create_psv_in, in, num_psv);
834 static bool devx_is_obj_modify_cmd(const void *in)
836 	u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
869 		u16 op_mod = MLX5_GET(set_fte_in, in, op_mod);
880 static bool devx_is_obj_query_cmd(const void *in)
882 	u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
916 static bool devx_is_whitelist_cmd(void *in)
918 	u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
952 static bool devx_is_general_cmd(void *in, struct mlx5_ib_dev *dev)
954 	u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
956 	/* Pass all cmds for vhca_tunnel as general, tracking is done in FW */
958 	     MLX5_GET(general_obj_in_cmd_hdr, in, vhca_tunnel_id)) ||
1019  * is subject to UAR doorbells (QP/SQ/CQ) gets a UAR ID (called uar_page in
1026  * Now in devx, as the devx kernel does not manipulate the QP/SQ/CQ command
1028  * ID, so it can embed it in these objects in the expected specification
1030  * QP/SQ/CQ with a UAR ID other than his, and then in this case other users
1107 static void devx_obj_build_destroy_cmd(void *in, void *out, void *din,
1111 	u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode);
1112 	u16 uid = MLX5_GET(general_obj_in_cmd_hdr, in, uid);
1114 	*obj_id = devx_get_created_obj_id(in, out, opcode);
1123 			 MLX5_GET(general_obj_in_cmd_hdr, in, obj_type));
1182 			 MLX5_GET(create_flow_table_in,  in, other_vport));
1184 			 MLX5_GET(create_flow_table_in,  in, vport_number));
1186 			 MLX5_GET(create_flow_table_in,  in, table_type));
1194 			 MLX5_GET(create_flow_group_in, in, other_vport));
1196 			 MLX5_GET(create_flow_group_in, in, vport_number));
1198 			 MLX5_GET(create_flow_group_in, in, table_type));
1200 			 MLX5_GET(create_flow_group_in, in, table_id));
1208 			 MLX5_GET(set_fte_in,  in, other_vport));
1210 			 MLX5_GET(set_fte_in, in, vport_number));
1212 			 MLX5_GET(set_fte_in, in, table_type));
1214 			 MLX5_GET(set_fte_in, in, table_id));
1241 			 MLX5_GET(create_scheduling_element_in, in,
1284 			 MLX5_GET(attach_to_mcg_in, in, qpn));
1286 		       MLX5_ADDR_OF(attach_to_mcg_in, in, multicast_gid),
1311 				     void *in, void *out)
1317 	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1330 				   void *in, int in_len)
1341 	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1353 	MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1);
1452 static bool is_apu_cq(struct mlx5_ib_dev *dev, const void *in)
1455 	    !MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), apu_cq))
2263 	 * If the user does not pass in pgsz_bitmap then the user promises not
2264 	 * to use umem_offset!=0 in any commands that allocate on top of the
2267 	 * If the user wants to use a umem_offset then it must pass in
2288 	cmd->in = uverbs_zalloc(attrs, cmd->inlen);
2289 	if (IS_ERR(cmd->in))
2290 		return PTR_ERR(cmd->in);
2292 	umem = MLX5_ADDR_OF(create_umem_in, cmd->in, umem);
2295 	MLX5_SET(create_umem_in, cmd->in, opcode, MLX5_CMD_OP_CREATE_UMEM);
2350 	MLX5_SET(create_umem_in, cmd.in, uid, c->devx_uid);
2351 	err = mlx5_cmd_exec(dev->mdev, cmd.in, cmd.inlen, cmd.out,
2358 	devx_obj_build_destroy_cmd(cmd.in, cmd.out, obj->dinbox, &obj->dinlen, &obj_id);