hw/irdma/hw.c

134 static void irdma_set_flush_fields(struct irdma_sc_qp *qp,
137 	qp->sq_flush_code = info->sq;
138 	qp->rq_flush_code = info->rq;
139 	qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
152 		qp->flush_code = FLUSH_PROT_ERR;
153 		qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
157 		qp->flush_code = FLUSH_LOC_QP_OP_ERR;
158 		qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
165 		qp->flush_code = FLUSH_LOC_LEN_ERR;
166 		qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
170 		qp->flush_code = FLUSH_REM_ACCESS_ERR;
171 		qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
177 		qp->flush_code = FLUSH_REM_OP_ERR;
178 		qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
181 		qp->flush_code = FLUSH_FATAL_ERR;
182 		qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
185 		qp->flush_code = FLUSH_GENERAL_ERR;
188 		qp->flush_code = FLUSH_RETRY_EXC_ERR;
189 		qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
195 		qp->flush_code = FLUSH_MW_BIND_ERR;
196 		qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
199 		qp->flush_code = FLUSH_REM_INV_REQ_ERR;
200 		qp->event_type = IRDMA_QP_EVENT_REQ_ERR;
203 		qp->flush_code = FLUSH_GENERAL_ERR;
204 		qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
223 	struct irdma_sc_qp *qp = NULL;
241 			  "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n",
242 			  info->ae_id, info->qp, info->qp_cq_id, info->tcp_state,
245 		if (info->qp) {
262 			qp = &iwqp->sc_qp;
288 			if (qp->term_flags)
306 			if (qp->term_flags)
307 				irdma_terminate_done(qp, 0);
324 				if (!atomic_dec_return(&qp->vsi->qp_suspend_reqs))
333 			irdma_terminate_send_fin(qp);
336 			irdma_terminate_received(qp, info);
394 			ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n",
395 				  info->ae_id, info->qp, info->qp_cq_id, info->ae_src);
403 				irdma_set_flush_fields(qp, info);
420 				irdma_terminate_connection(qp, info);
424 		if (info->qp)
584  * irdma_destroy_cqp  - destroy control qp
921  * irdma_create_cqp - create control qp
1871 		/* handles asynch cleanup tasks - disconnect CM , free qp,
2049 	set_bit(2, rf->allocated_qps); /* qp 2 IEQ */
2050 	set_bit(1, rf->allocated_qps); /* qp 1 ILQ */
2159  * irdma_next_iw_state - modify qp state
2160  * @iwqp: iwarp qp to modify
2161  * @state: next state for qp
2548 	struct irdma_sc_qp *qp;
2554 	qp = cqp_info->in.u.qp_flush_wqes.qp;
2555 	iwqp = qp->qp_uk.back_qp;
2564 		qp->qp_uk.rq_flush_complete = true;
2569 		if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2571 				  qp->qp_uk.qp_id);
2574 		qp->qp_uk.sq_flush_complete = true;
2579  * irdma_hw_flush_wqes - flush qp's wqe
2581  * @qp: hardware control qp
2585 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2592 	struct irdma_qp *iwqp = qp->qp_uk.back_qp;
2605 	cqp_info->in.u.qp_flush_wqes.qp = qp;
2609 		qp->qp_uk.sq_flush_complete = true;
2610 		qp->qp_uk.rq_flush_complete = true;
2622 			qp->qp_uk.rq_flush_complete = true;
2632 			if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2635 				if (!qp->qp_uk.sq_flush_complete)
2637 				qp->qp_uk.sq_flush_complete = false;
2638 				qp->flush_sq = false;
2652 				cqp_info->in.u.qp_flush_wqes.qp = qp;
2659 					ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d",
2661 					qp->qp_uk.sq_flush_complete = false;
2667 				qp->qp_uk.sq_flush_complete = true;
2670 			if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring))
2671 				qp->qp_uk.sq_flush_complete = true;
2690  * @qp: qp associated with AE
2694 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2710 	cqp_info->in.u.gen_ae.qp = qp;