hw/hfi1/mad.c

870 	pi->vl.cap = ppd->vls_supported;
871 	pi->vl.high_limit = cpu_to_be16(ibp->rvp.vl_high_limit);
872 	pi->vl.arb_high_cap = (u8)hfi1_get_ib_cfg(ppd, HFI1_IB_CFG_VL_HIGH_CAP);
873 	pi->vl.arb_low_cap = (u8)hfi1_get_ib_cfg(ppd, HFI1_IB_CFG_VL_LOW_CAP);
1480 	ibp->rvp.vl_high_limit = be16_to_cpu(pi->vl.high_limit) & 0xFF;
1505 				    "MTU change on vl %d from %d to %d\n",
1519 			    "MTU change on vl 15 from %d to %d\n",
2588 		unsigned long vl;
2592 		for_each_set_bit(vl, &vl_all_mask, BITS_PER_LONG) {
2595 						 idx_from_vl(vl));
2639  * @vl: represent VL0-VL7, VL15 for PortVLXmitWait counters request
2640  * and if vl value is C_VL_COUNT, it represent SendWaitCnt
2642  * @return: return SendWaitCnt/SendWaitVlCnt counter value per vl.
2651 			   u16 link_width, u16 link_speed, int vl)
2657 	if (vl > C_VL_COUNT)
2659 	if (vl < C_VL_COUNT)
2661 			read_port_cntr(ppd, C_TX_WAIT_VL, vl);
2668 		ppd->port_vl_xmit_wait_last[vl];
2674 	ppd->vl_xmit_flit_cnt[vl] += delta_vl_xmit_wait;
2675 	ppd->port_vl_xmit_wait_last[vl] = port_vl_xmit_wait_curr;
2678 	return ppd->vl_xmit_flit_cnt[vl];
2690 	unsigned long vl;
2798 	 * any additional checks for vl.
2800 	for_each_set_bit(vl, &vl_select_mask, BITS_PER_LONG) {
2803 		tmp = read_dev_cntr(dd, C_DC_RX_FLIT_VL, idx_from_vl(vl));
2808 						  idx_from_vl(vl)));
2812 						   idx_from_vl(vl)));
2816 						   idx_from_vl(vl)));
2824 							   idx_from_vl(vl)));
2828 						  idx_from_vl(vl)));
2832 						  idx_from_vl(vl)));
2836 						   idx_from_vl(vl)));
2891 		unsigned long vl;
2895 		for_each_set_bit(vl, &vl_all_mask, BITS_PER_LONG) {
2898 						 idx_from_vl(vl));
2949 	unsigned long vl;
3025 	 * any additional checks for vl.
3027 	for_each_set_bit(vl, &vl_select_mask, BITS_PER_LONG) {
3032 						   idx_from_vl(vl)));
3036 						  idx_from_vl(vl)));
3040 						   idx_from_vl(vl)));
3044 						  idx_from_vl(vl)));
3053 							   idx_from_vl(vl)));
3057 						  idx_from_vl(vl)));
3060 						  idx_from_vl(vl)));
3168 	unsigned long vl;
3228 	for_each_set_bit(vl, &vl_select_mask, BITS_PER_LONG) {
3232 						   idx_from_vl(vl)));
3439 	unsigned long vl_select_mask = VL_MASK_ALL; /* clear all per-vl cnts */
3440 	unsigned long vl;
3533 	for_each_set_bit(vl, &vl_select_mask, BITS_PER_LONG) {
3535 			write_port_cntr(ppd, C_TX_FLIT_VL, idx_from_vl(vl), 0);
3538 			write_dev_cntr(dd, C_DC_RX_FLIT_VL, idx_from_vl(vl), 0);
3541 			write_port_cntr(ppd, C_TX_PKT_VL, idx_from_vl(vl), 0);
3544 			write_dev_cntr(dd, C_DC_RX_PKT_VL, idx_from_vl(vl), 0);
3547 			write_port_cntr(ppd, C_TX_WAIT_VL, idx_from_vl(vl), 0);
3548 			ppd->port_vl_xmit_wait_last[idx_from_vl(vl)] = 0;
3549 			ppd->vl_xmit_flit_cnt[idx_from_vl(vl)] = 0;
3554 			write_dev_cntr(dd, C_DC_RCV_FCN_VL, idx_from_vl(vl), 0);
3557 			write_dev_cntr(dd, C_DC_RCV_BCN_VL, idx_from_vl(vl), 0);
3563 			write_dev_cntr(dd, C_DC_RCV_BBL_VL, idx_from_vl(vl), 0);
3570 					idx_from_vl(vl), 0);