infiniband/core/rw.c

81 		reg->inv_wr.next = &reg->reg_wr.wr;
112 	reg->reg_wr.wr.opcode = IB_WR_REG_MR;
152 				prev->wr.wr.next = &reg->inv_wr;
154 				prev->wr.wr.next = &reg->reg_wr.wr;
157 		reg->reg_wr.wr.next = &reg->wr.wr;
159 		reg->wr.wr.sg_list = &reg->sge;
160 		reg->wr.wr.num_sge = 1;
161 		reg->wr.remote_addr = remote_addr;
162 		reg->wr.rkey = rkey;
164 			reg->wr.wr.opcode = IB_WR_RDMA_WRITE;
166 			reg->wr.wr.opcode = IB_WR_RDMA_READ;
168 			reg->wr.wr.opcode = IB_WR_RDMA_READ_WITH_INV;
169 			reg->wr.wr.ex.invalidate_rkey = reg->mr->lkey;
182 		prev->wr.wr.next = NULL;
219 			rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
221 			rdma_wr->wr.opcode = IB_WR_RDMA_READ;
224 		rdma_wr->wr.num_sge = nr_sge;
225 		rdma_wr->wr.sg_list = sge;
238 		rdma_wr->wr.next = i + 1 < ctx->nr_ops ?
239 			&ctx->map.wrs[i + 1].wr : NULL;
255 	struct ib_rdma_wr *rdma_wr = &ctx->single.wr;
265 		rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
267 		rdma_wr->wr.opcode = IB_WR_RDMA_READ;
268 	rdma_wr->wr.sg_list = &ctx->single.sge;
269 	rdma_wr->wr.num_sge = 1;
426 	ctx->reg->reg_wr.wr.opcode = IB_WR_REG_MR_INTEGRITY;
427 	ctx->reg->reg_wr.wr.wr_cqe = NULL;
428 	ctx->reg->reg_wr.wr.num_sge = 0;
429 	ctx->reg->reg_wr.wr.send_flags = 0;
442 	rdma_wr = &ctx->reg->wr;
443 	rdma_wr->wr.sg_list = &ctx->reg->sge;
444 	rdma_wr->wr.num_sge = 1;
448 		rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
450 		rdma_wr->wr.opcode = IB_WR_RDMA_READ;
451 	ctx->reg->reg_wr.wr.next = &rdma_wr->wr;
508 				ctx->reg[i].wr.wr.opcode !=
515 			first_wr = &ctx->reg[0].reg_wr.wr;
516 		last_wr = &ctx->reg[ctx->nr_ops - 1].wr.wr;
519 		first_wr = &ctx->map.wrs[0].wr;
520 		last_wr = &ctx->map.wrs[ctx->nr_ops - 1].wr;
523 		first_wr = &ctx->single.wr.wr;
524 		last_wr = &ctx->single.wr.wr;