iio/frequency/ad9523.c

170 #define AD9523_CLK_DIST_DIV_PHASE_REV(x)	((ret >> 18) & 0x3F)
172 #define AD9523_CLK_DIST_DIV_REV(x)		(((ret >> 8) & 0x3FF) + 1)
301 	int ret;
322 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
323 	if (ret < 0)
324 		dev_err(&indio_dev->dev, "read failed (%d)", ret);
326 		ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >>
329 	return ret;
336 	int ret;
352 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
354 	if (ret < 0)
355 		dev_err(&indio_dev->dev, "write failed (%d)", ret);
357 	return ret;
369 	int ret;
374 		ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
375 		if (ret < 0)
379 			ret |= mask;
382 			ret &= ~mask;
384 		ret = ad9523_write(indio_dev,
385 				   AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
388 		ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL);
389 		if (ret < 0)
393 			ret |= mask;
395 			ret &= ~mask;
396 		ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret);
399 		ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
400 		if (ret < 0)
404 			ret |= mask;
406 			ret &= ~mask;
407 		ret = ad9523_write(indio_dev,
408 				   AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
416 	return ret;
447 	int ret, tmp;
449 	ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1,
451 	if (ret < 0)
452 		return ret;
453 	ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2,
455 	if (ret < 0)
456 		return ret;
461 		ret = ad9523_read(indio_dev,
463 		if (ret < 0)
464 			return ret;
465 	} while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--);
467 	ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0);
468 	if (ret < 0)
469 		return ret;
471 	ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK);
472 	if (ret < 0)
473 		return ret;
475 	if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) {
477 		ret = -EIO;
480 	return ret;
485 	int ret, tmp;
487 	ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS);
488 	if (ret < 0)
489 		return ret;
491 	tmp = ret;
494 	ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
495 	if (ret < 0)
496 		return ret;
501 	ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
502 	if (ret < 0)
503 		return ret;
516 	int ret;
518 	ret = kstrtobool(buf, &state);
519 	if (ret < 0)
520 		return ret;
528 		ret = ad9523_sync(indio_dev);
531 		ret = ad9523_store_eeprom(indio_dev);
534 		ret = -ENODEV;
538 	return ret ? ret : len;
548 	int ret;
551 	ret = ad9523_read(indio_dev, AD9523_READBACK_0);
552 	if (ret >= 0) {
553 		ret = sysfs_emit(buf, "%d\n", !!(ret & (1 <<
558 	return ret;
637 	int ret;
640 	ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
643 	if (ret < 0)
644 		return ret;
648 		*val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN);
652 			AD9523_CLK_DIST_DIV_REV(ret);
655 		code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) /
656 			AD9523_CLK_DIST_DIV_REV(ret);
673 	int ret, tmp, code;
676 	ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
677 	if (ret < 0)
680 	reg = ret;
691 			ret = -EINVAL;
694 		ret = ad9523_set_clock_provider(indio_dev, chan->channel, val);
695 		if (ret < 0)
704 		tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592;
710 		ret = -EINVAL;
714 	ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel),
716 	if (ret < 0)
722 	return ret;
730 	int ret;
734 		ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);
737 		ret = ad9523_read(indio_dev, reg | AD9523_R1B);
738 		if (ret < 0)
740 		*readval = ret;
741 		ret = 0;
747 	return ret;
763 	int ret, i;
765 	ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG,
769 	if (ret < 0)
770 		return ret;
772 	ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL,
774 	if (ret < 0)
775 		return ret;
777 	ret = ad9523_io_update(indio_dev);
778 	if (ret < 0)
779 		return ret;
784 	ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER,
786 	if (ret < 0)
787 		return ret;
789 	ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER,
791 	if (ret < 0)
792 		return ret;
794 	ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER,
796 	if (ret < 0)
797 		return ret;
799 	ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL,
804 	if (ret < 0)
805 		return ret;
807 	ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,
815 	if (ret < 0)
816 		return ret;
818 	ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL,
827 	if (ret < 0)
828 		return ret;
830 	ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL,
833 	if (ret < 0)
834 		return ret;
836 	ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL,
838 	if (ret < 0)
839 		return ret;
844 	ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP,
847 	if (ret < 0)
848 		return ret;
850 	ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,
853 	if (ret < 0)
854 		return ret;
856 	ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL,
860 	if (ret < 0)
861 		return ret;
869 	ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL,
871 	if (ret < 0)
872 		return ret;
874 	ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
881 	if (ret < 0)
882 		return ret;
894 	ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER,
896 	if (ret < 0)
897 		return ret;
899 	ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL,
905 	if (ret < 0)
906 		return ret;
912 			ret = ad9523_write(indio_dev,
925 			if (ret < 0)
926 				return ret;
928 			ret = ad9523_vco_out_map(indio_dev, chan->channel_num,
930 			if (ret < 0)
931 				return ret;
947 		ret = ad9523_write(indio_dev,
951 		if (ret < 0)
952 			return ret;
955 	ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0);
956 	if (ret < 0)
957 		return ret;
959 	ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS,
961 	if (ret < 0)
962 		return ret;
964 	ret = ad9523_io_update(indio_dev);
965 	if (ret < 0)
966 		return ret;
976 	int ret;
991 	ret = devm_regulator_get_enable(&spi->dev, "vcc");
992 	if (ret)
993 		return ret;
1026 	ret = ad9523_setup(indio_dev);
1027 	if (ret < 0)
1028 		return ret;