Lines Matching refs:indio_dev

161 static int ads124s_write_cmd(struct iio_dev *indio_dev, u8 command)
163 struct ads124s_private *priv = iio_priv(indio_dev);
170 static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data)
172 struct ads124s_private *priv = iio_priv(indio_dev);
181 static int ads124s_reset(struct iio_dev *indio_dev)
183 struct ads124s_private *priv = iio_priv(indio_dev);
190 return ads124s_write_cmd(indio_dev, ADS124S08_CMD_RESET);
196 static int ads124s_read(struct iio_dev *indio_dev)
198 struct ads124s_private *priv = iio_priv(indio_dev);
222 static int ads124s_read_raw(struct iio_dev *indio_dev,
226 struct ads124s_private *priv = iio_priv(indio_dev);
232 ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
239 ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
245 ret = ads124s_read(indio_dev);
253 ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
277 struct iio_dev *indio_dev = pf->indio_dev;
278 struct ads124s_private *priv = iio_priv(indio_dev);
282 for_each_set_bit(scan_index, indio_dev->active_scan_mask,
283 indio_dev->masklength) {
284 ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
289 ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
293 priv->buffer[j] = ads124s_read(indio_dev);
294 ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
301 iio_push_to_buffers_with_timestamp(indio_dev, priv->buffer,
304 iio_trigger_notify_done(indio_dev->trig);
312 struct iio_dev *indio_dev;
316 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ads124s_priv));
317 if (indio_dev == NULL)
320 ads124s_priv = iio_priv(indio_dev);
331 indio_dev->name = spi_id->name;
332 indio_dev->modes = INDIO_DIRECT_MODE;
333 indio_dev->channels = ads124s_priv->chip_info->channels;
334 indio_dev->num_channels = ads124s_priv->chip_info->num_channels;
335 indio_dev->info = &ads124s_info;
339 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
346 ads124s_reset(indio_dev);
348 return devm_iio_device_register(&spi->dev, indio_dev);