iio/adc/mt6360-adc.c

66 static int mt6360_adc_read_channel(struct mt6360_adc_data *mad, int channel, int *val)
74 	mutex_lock(&mad->adc_lock);
77 	ret = regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK,
83 	ret = regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));
87 	predict_end_t = ktime_add_ms(mad->last_off_timestamps[channel], 2 * ADC_WAIT_TIME_MS);
101 		ret = regmap_raw_read(mad->regmap, MT6360_REG_PMUADCRPT1, rpt, sizeof(rpt));
133 	regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable));
134 	mad->last_off_timestamps[channel] = ktime_get();
136 	regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK,
139 	mutex_unlock(&mad->adc_lock);
144 static int mt6360_adc_read_scale(struct mt6360_adc_data *mad, int channel, int *val, int *val2)
169 			ret = regmap_read(mad->regmap, MT6360_REG_PMUCHGCTRL3, &regval);
188 static int mt6360_adc_read_offset(struct mt6360_adc_data *mad, int channel, int *val)
197 	struct mt6360_adc_data *mad = iio_priv(iio_dev);
201 		return mt6360_adc_read_channel(mad, chan->channel, val);
203 		return mt6360_adc_read_scale(mad, chan->channel, val, val2);
205 		return mt6360_adc_read_offset(mad, chan->channel, val);
263 	struct mt6360_adc_data *mad = iio_priv(indio_dev);
272 		ret = mt6360_adc_read_channel(mad, bit, &val);
314 	struct mt6360_adc_data *mad;
325 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*mad));
329 	mad = iio_priv(indio_dev);
330 	mad->dev = &pdev->dev;
331 	mad->regmap = regmap;
332 	mutex_init(&mad->adc_lock);
334 	ret = mt6360_adc_reset(mad);