Lines Matching refs:master
3 * Silvaco dual-role I3C master driver
14 #include <linux/i3c/master.h>
161 * @base: I3C master controller
183 * @lock: Transfer lock, protect between IBI work thread and callbacks from master
219 * @index: Index in the master tables corresponding to this device
220 * @ibi: IBI slot index in the master structure
229 static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask)
231 return !!(master->enabled_events & mask);
234 static bool svc_i3c_master_error(struct svc_i3c_master *master)
238 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
240 merrwarn = readl(master->regs + SVC_I3C_MERRWARN);
241 writel(merrwarn, master->regs + SVC_I3C_MERRWARN);
245 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n",
250 dev_err(master->dev,
260 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask)
262 writel(mask, master->regs + SVC_I3C_MINTSET);
265 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master)
267 u32 mask = readl(master->regs + SVC_I3C_MINTSET);
269 writel(mask, master->regs + SVC_I3C_MINTCLR);
272 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master)
275 writel(readl(master->regs + SVC_I3C_MERRWARN),
276 master->regs + SVC_I3C_MERRWARN);
279 static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master)
283 master->regs + SVC_I3C_MDATACTRL);
286 static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master)
296 writel(reg, master->regs + SVC_I3C_MDATACTRL);
299 static void svc_i3c_master_reset(struct svc_i3c_master *master)
301 svc_i3c_master_clear_merrwarn(master);
302 svc_i3c_master_reset_fifo_trigger(master);
303 svc_i3c_master_disable_interrupts(master);
307 to_svc_i3c_master(struct i3c_master_controller *master)
309 return container_of(master, struct svc_i3c_master, base);
314 struct svc_i3c_master *master;
316 master = container_of(work, struct svc_i3c_master, hj_work);
317 i3c_master_do_daa(&master->base);
321 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master,
327 if (master->addrs[i] == ibiaddr)
333 return master->descs[i];
336 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master)
338 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL);
349 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master,
366 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
369 dev_err(master->dev, "Timeout when polling for COMPLETE\n");
373 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) &&
375 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);
377 readsl(master->regs + SVC_I3C_MRDATAB, buf, count);
382 master->ibi.tbq_slot = slot;
387 static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master,
398 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL);
401 static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master)
405 master->regs + SVC_I3C_MCTRL);
410 struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work);
417 mutex_lock(&master->lock);
421 master->regs + SVC_I3C_MCTRL);
424 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
427 dev_err(master->dev, "Timeout when polling for IBIWON\n");
428 svc_i3c_master_emit_stop(master);
433 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
435 status = readl(master->regs + SVC_I3C_MSTATUS);
442 dev = svc_i3c_master_dev_from_addr(master, ibiaddr);
443 if (!dev || !is_events_enabled(master, SVC_I3C_EVENT_IBI))
444 svc_i3c_master_nack_ibi(master);
446 svc_i3c_master_handle_ibi(master, dev);
449 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN))
450 svc_i3c_master_ack_ibi(master, false);
452 svc_i3c_master_nack_ibi(master);
455 svc_i3c_master_nack_ibi(master);
466 if (svc_i3c_master_error(master)) {
467 if (master->ibi.tbq_slot) {
470 master->ibi.tbq_slot);
471 master->ibi.tbq_slot = NULL;
474 svc_i3c_master_emit_stop(master);
483 i3c_master_queue_ibi(dev, master->ibi.tbq_slot);
484 master->ibi.tbq_slot = NULL;
486 svc_i3c_master_emit_stop(master);
489 svc_i3c_master_emit_stop(master);
490 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN))
491 queue_work(master->base.wq, &master->hj_work);
499 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
500 mutex_unlock(&master->lock);
505 struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id;
506 u32 active = readl(master->regs + SVC_I3C_MSTATUS);
512 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
514 svc_i3c_master_disable_interrupts(master);
517 queue_work(master->base.wq, &master->ibi_work);
524 struct svc_i3c_master *master = to_svc_i3c_master(m);
532 ret = pm_runtime_resume_and_get(master->dev);
534 dev_err(master->dev,
535 "<%s> cannot resume i3c bus master, err: %d\n",
541 fclk_rate = clk_get_rate(master->fclk);
602 writel(reg, master->regs + SVC_I3C_MCONFIG);
612 master->regs + SVC_I3C_MDYNADDR);
614 ret = i3c_master_set_info(&master->base, &info);
619 pm_runtime_mark_last_busy(master->dev);
620 pm_runtime_put_autosuspend(master->dev);
627 struct svc_i3c_master *master = to_svc_i3c_master(m);
630 ret = pm_runtime_resume_and_get(master->dev);
632 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
636 svc_i3c_master_disable_interrupts(master);
638 /* Disable master */
639 writel(0, master->regs + SVC_I3C_MCONFIG);
641 pm_runtime_mark_last_busy(master->dev);
642 pm_runtime_put_autosuspend(master->dev);
645 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master)
649 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0)))
652 slot = ffs(master->free_slots) - 1;
654 master->free_slots &= ~BIT(slot);
659 static void svc_i3c_master_release_slot(struct svc_i3c_master *master,
662 master->free_slots |= BIT(slot);
668 struct svc_i3c_master *master = to_svc_i3c_master(m);
672 slot = svc_i3c_master_reserve_slot(master);
678 svc_i3c_master_release_slot(master, slot);
684 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr :
686 master->descs[slot] = dev;
697 struct svc_i3c_master *master = to_svc_i3c_master(m);
700 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr :
710 struct svc_i3c_master *master = to_svc_i3c_master(m);
712 master->addrs[data->index] = 0;
713 svc_i3c_master_release_slot(master, data->index);
721 struct svc_i3c_master *master = to_svc_i3c_master(m);
725 slot = svc_i3c_master_reserve_slot(master);
731 svc_i3c_master_release_slot(master, slot);
736 master->addrs[slot] = dev->addr;
747 struct svc_i3c_master *master = to_svc_i3c_master(m);
749 svc_i3c_master_release_slot(master, data->index);
754 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst,
761 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
768 dst[i] = readl(master->regs + SVC_I3C_MRDATAB);
774 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master,
788 master->regs + SVC_I3C_MCTRL);
794 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
810 ret = svc_i3c_master_readb(master, data, 6);
818 ret = svc_i3c_master_readb(master, data, 2);
847 svc_i3c_master_emit_stop(master);
856 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
866 ret = i3c_master_get_free_addr(&master->base, last_addr + 1);
871 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n",
874 writel(addrs[dev_nb], master->regs + SVC_I3C_MWDATAB);
883 static int svc_i3c_update_ibirules(struct svc_i3c_master *master)
892 i3c_bus_for_each_i3cdev(&master->base.bus, dev) {
930 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES);
932 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES);
939 struct svc_i3c_master *master = to_svc_i3c_master(m);
945 ret = pm_runtime_resume_and_get(master->dev);
947 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
951 spin_lock_irqsave(&master->xferqueue.lock, flags);
952 ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb);
953 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
955 svc_i3c_master_emit_stop(master);
956 svc_i3c_master_clear_merrwarn(master);
968 ret = svc_i3c_update_ibirules(master);
970 dev_err(master->dev, "Cannot handle such a list of devices");
973 pm_runtime_mark_last_busy(master->dev);
974 pm_runtime_put_autosuspend(master->dev);
979 static int svc_i3c_master_read(struct svc_i3c_master *master,
989 mstatus = readl(master->regs + SVC_I3C_MSTATUS);
994 dev_dbg(master->dev, "I3C read timeout\n");
998 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL);
1001 dev_err(master->dev, "I3C receive length too long!\n");
1005 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB);
1013 static int svc_i3c_master_write(struct svc_i3c_master *master,
1020 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL,
1032 writel(out[offset++], master->regs + SVC_I3C_MWDATAB);
1034 writel(out[offset++], master->regs + SVC_I3C_MWDATABE);
1040 static int svc_i3c_master_xfer(struct svc_i3c_master *master,
1049 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
1057 master->regs + SVC_I3C_MCTRL);
1059 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1064 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
1089 ret = svc_i3c_master_read(master, in, xfer_len);
1091 ret = svc_i3c_master_write(master, out, xfer_len);
1098 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1103 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS);
1106 svc_i3c_master_emit_stop(master);
1109 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1116 svc_i3c_master_emit_stop(master);
1117 svc_i3c_master_clear_merrwarn(master);
1123 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds)
1143 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master,
1146 if (master->xferqueue.cur == xfer)
1147 master->xferqueue.cur = NULL;
1152 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master,
1157 spin_lock_irqsave(&master->xferqueue.lock, flags);
1158 svc_i3c_master_dequeue_xfer_locked(master, xfer);
1159 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1162 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master)
1164 struct svc_i3c_xfer *xfer = master->xferqueue.cur;
1170 svc_i3c_master_clear_merrwarn(master);
1171 svc_i3c_master_flush_fifo(master);
1176 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type,
1192 svc_i3c_master_dequeue_xfer_locked(master, xfer);
1194 xfer = list_first_entry_or_null(&master->xferqueue.list,
1200 master->xferqueue.cur = xfer;
1201 svc_i3c_master_start_xfer_locked(master);
1204 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master,
1210 ret = pm_runtime_resume_and_get(master->dev);
1212 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1217 spin_lock_irqsave(&master->xferqueue.lock, flags);
1218 if (master->xferqueue.cur) {
1219 list_add_tail(&xfer->node, &master->xferqueue.list);
1221 master->xferqueue.cur = xfer;
1222 svc_i3c_master_start_xfer_locked(master);
1224 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1226 pm_runtime_mark_last_busy(master->dev);
1227 pm_runtime_put_autosuspend(master->dev);
1231 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master,
1238 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master,
1247 xfer = svc_i3c_master_alloc_xfer(master, 1);
1271 mutex_lock(&master->lock);
1272 svc_i3c_master_enqueue_xfer(master, xfer);
1274 svc_i3c_master_dequeue_xfer(master, xfer);
1275 mutex_unlock(&master->lock);
1284 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master,
1293 xfer = svc_i3c_master_alloc_xfer(master, 2);
1319 mutex_lock(&master->lock);
1320 svc_i3c_master_enqueue_xfer(master, xfer);
1322 svc_i3c_master_dequeue_xfer(master, xfer);
1323 mutex_unlock(&master->lock);
1337 struct svc_i3c_master *master = to_svc_i3c_master(m);
1342 ret = svc_i3c_master_send_bdcast_ccc_cmd(master, cmd);
1344 ret = svc_i3c_master_send_direct_ccc_cmd(master, cmd);
1357 struct svc_i3c_master *master = to_svc_i3c_master(m);
1362 xfer = svc_i3c_master_alloc_xfer(master, nxfers);
1372 cmd->addr = master->addrs[data->index];
1381 mutex_lock(&master->lock);
1382 svc_i3c_master_enqueue_xfer(master, xfer);
1384 svc_i3c_master_dequeue_xfer(master, xfer);
1385 mutex_unlock(&master->lock);
1398 struct svc_i3c_master *master = to_svc_i3c_master(m);
1403 xfer = svc_i3c_master_alloc_xfer(master, nxfers);
1412 cmd->addr = master->addrs[data->index];
1421 mutex_lock(&master->lock);
1422 svc_i3c_master_enqueue_xfer(master, xfer);
1424 svc_i3c_master_dequeue_xfer(master, xfer);
1425 mutex_unlock(&master->lock);
1437 struct svc_i3c_master *master = to_svc_i3c_master(m);
1443 dev_err(master->dev, "IBI max payload %d should be < %d\n",
1452 spin_lock_irqsave(&master->ibi.lock, flags);
1453 for (i = 0; i < master->ibi.num_slots; i++) {
1454 if (!master->ibi.slots[i]) {
1456 master->ibi.slots[i] = dev;
1460 spin_unlock_irqrestore(&master->ibi.lock, flags);
1462 if (i < master->ibi.num_slots)
1474 struct svc_i3c_master *master = to_svc_i3c_master(m);
1478 spin_lock_irqsave(&master->ibi.lock, flags);
1479 master->ibi.slots[data->ibi] = NULL;
1481 spin_unlock_irqrestore(&master->ibi.lock, flags);
1489 struct svc_i3c_master *master = to_svc_i3c_master(m);
1492 ret = pm_runtime_resume_and_get(master->dev);
1494 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1498 master->enabled_events |= SVC_I3C_EVENT_IBI;
1499 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
1507 struct svc_i3c_master *master = to_svc_i3c_master(m);
1510 master->enabled_events &= ~SVC_I3C_EVENT_IBI;
1511 if (!master->enabled_events)
1512 svc_i3c_master_disable_interrupts(master);
1516 pm_runtime_mark_last_busy(master->dev);
1517 pm_runtime_put_autosuspend(master->dev);
1524 struct svc_i3c_master *master = to_svc_i3c_master(m);
1527 ret = pm_runtime_resume_and_get(master->dev);
1529 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1533 master->enabled_events |= SVC_I3C_EVENT_HOTJOIN;
1535 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
1542 struct svc_i3c_master *master = to_svc_i3c_master(m);
1544 master->enabled_events &= ~SVC_I3C_EVENT_HOTJOIN;
1546 if (!master->enabled_events)
1547 svc_i3c_master_disable_interrupts(master);
1549 pm_runtime_mark_last_busy(master->dev);
1550 pm_runtime_put_autosuspend(master->dev);
1585 static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master)
1589 ret = clk_prepare_enable(master->pclk);
1593 ret = clk_prepare_enable(master->fclk);
1595 clk_disable_unprepare(master->pclk);
1599 ret = clk_prepare_enable(master->sclk);
1601 clk_disable_unprepare(master->pclk);
1602 clk_disable_unprepare(master->fclk);
1609 static void svc_i3c_master_unprepare_clks(struct svc_i3c_master *master)
1611 clk_disable_unprepare(master->pclk);
1612 clk_disable_unprepare(master->fclk);
1613 clk_disable_unprepare(master->sclk);
1619 struct svc_i3c_master *master;
1622 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
1623 if (!master)
1626 master->regs = devm_platform_ioremap_resource(pdev, 0);
1627 if (IS_ERR(master->regs))
1628 return PTR_ERR(master->regs);
1630 master->pclk = devm_clk_get(dev, "pclk");
1631 if (IS_ERR(master->pclk))
1632 return PTR_ERR(master->pclk);
1634 master->fclk = devm_clk_get(dev, "fast_clk");
1635 if (IS_ERR(master->fclk))
1636 return PTR_ERR(master->fclk);
1638 master->sclk = devm_clk_get(dev, "slow_clk");
1639 if (IS_ERR(master->sclk))
1640 return PTR_ERR(master->sclk);
1642 master->irq = platform_get_irq(pdev, 0);
1643 if (master->irq < 0)
1644 return master->irq;
1646 master->dev = dev;
1648 ret = svc_i3c_master_prepare_clks(master);
1652 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work);
1653 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work);
1654 mutex_init(&master->lock);
1656 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler,
1657 IRQF_NO_SUSPEND, "svc-i3c-irq", master);
1661 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0);
1663 spin_lock_init(&master->xferqueue.lock);
1664 INIT_LIST_HEAD(&master->xferqueue.list);
1666 spin_lock_init(&master->ibi.lock);
1667 master->ibi.num_slots = SVC_I3C_MAX_DEVS;
1668 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1669 sizeof(*master->ibi.slots),
1671 if (!master->ibi.slots) {
1676 platform_set_drvdata(pdev, master);
1684 svc_i3c_master_reset(master);
1686 /* Register the master */
1687 ret = i3c_master_register(&master->base, &pdev->dev,
1704 svc_i3c_master_unprepare_clks(master);
1711 struct svc_i3c_master *master = platform_get_drvdata(pdev);
1713 i3c_master_unregister(&master->base);
1719 static void svc_i3c_save_regs(struct svc_i3c_master *master)
1721 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG);
1722 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR);
1725 static void svc_i3c_restore_regs(struct svc_i3c_master *master)
1727 if (readl(master->regs + SVC_I3C_MDYNADDR) !=
1728 master->saved_regs.mdynaddr) {
1729 writel(master->saved_regs.mconfig,
1730 master->regs + SVC_I3C_MCONFIG);
1731 writel(master->saved_regs.mdynaddr,
1732 master->regs + SVC_I3C_MDYNADDR);
1738 struct svc_i3c_master *master = dev_get_drvdata(dev);
1740 svc_i3c_save_regs(master);
1741 svc_i3c_master_unprepare_clks(master);
1749 struct svc_i3c_master *master = dev_get_drvdata(dev);
1752 svc_i3c_master_prepare_clks(master);
1754 svc_i3c_restore_regs(master);
1767 { .compatible = "silvaco,i3c-master-v1"},
1776 .name = "silvaco-i3c-master",
1785 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");