Lines Matching refs:master
13 #include <linux/i3c/master.h>
24 #include "dw-i3c-master.h"
290 to_dw_i3c_master(struct i3c_master_controller *master)
292 return container_of(master, struct dw_i3c_master, base);
295 static void dw_i3c_master_disable(struct dw_i3c_master *master)
297 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE,
298 master->regs + DEVICE_CTRL);
301 static void dw_i3c_master_enable(struct dw_i3c_master *master)
303 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE,
304 master->regs + DEVICE_CTRL);
307 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
311 for (pos = 0; pos < master->maxdevs; pos++) {
312 if (addr == master->devs[pos].addr)
319 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
321 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
324 return ffs(master->free_pos) - 1;
327 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
330 writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
335 writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
339 static void dw_i3c_master_read_fifo(struct dw_i3c_master *master,
342 readsl(master->regs + reg, bytes, nbytes / 4);
346 readsl(master->regs + reg, &tmp, 1);
351 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
354 return dw_i3c_master_read_fifo(master, RX_TX_DATA_PORT, bytes, nbytes);
357 static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master,
360 return dw_i3c_master_read_fifo(master, IBI_QUEUE_STATUS, bytes, nbytes);
364 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
384 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master)
386 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
396 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
399 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
402 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
407 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
408 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
412 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master,
418 spin_lock_irqsave(&master->xferqueue.lock, flags);
419 if (master->xferqueue.cur) {
420 list_add_tail(&xfer->node, &master->xferqueue.list);
422 master->xferqueue.cur = xfer;
423 dw_i3c_master_start_xfer_locked(master);
425 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
428 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master,
431 if (master->xferqueue.cur == xfer) {
434 master->xferqueue.cur = NULL;
438 master->regs + RESET_CTRL);
440 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status,
447 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master,
452 spin_lock_irqsave(&master->xferqueue.lock, flags);
453 dw_i3c_master_dequeue_xfer_locked(master, xfer);
454 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
457 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr)
459 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
466 nresp = readl(master->regs + QUEUE_STATUS_LEVEL);
473 resp = readl(master->regs + RESPONSE_QUEUE_PORT);
479 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf,
509 dw_i3c_master_dequeue_xfer_locked(master, xfer);
510 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
511 master->regs + DEVICE_CTRL);
514 xfer = list_first_entry_or_null(&master->xferqueue.list,
520 master->xferqueue.cur = xfer;
521 dw_i3c_master_start_xfer_locked(master);
524 static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
530 core_rate = clk_get_rate(master->core_clk);
540 lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt;
545 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
551 if (master->base.bus.mode == I3C_BUS_MODE_PURE)
552 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
557 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
567 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
572 static int dw_i2c_clk_cfg(struct dw_i3c_master *master)
578 core_rate = clk_get_rate(master->core_clk);
588 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
594 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
596 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
597 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
598 master->regs + DEVICE_CTRL);
605 struct dw_i3c_master *master = to_dw_i3c_master(m);
611 ret = master->platform_ops->init(master);
618 ret = dw_i2c_clk_cfg(master);
623 ret = dw_i3c_clk_cfg(master);
631 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
637 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
639 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
641 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
643 writel(INTR_ALL, master->regs + INTR_STATUS);
644 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
645 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
652 master->regs + DEVICE_ADDR);
657 ret = i3c_master_set_info(&master->base, &info);
661 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT);
662 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
665 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
666 master->regs + DEVICE_CTRL);
668 dw_i3c_master_enable(master);
675 struct dw_i3c_master *master = to_dw_i3c_master(m);
677 dw_i3c_master_disable(master);
680 static int dw_i3c_ccc_set(struct dw_i3c_master *master,
688 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
693 xfer = dw_i3c_master_alloc_xfer(master, 1);
710 dw_i3c_master_enqueue_xfer(master, xfer);
712 dw_i3c_master_dequeue_xfer(master, xfer);
723 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc)
729 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
733 xfer = dw_i3c_master_alloc_xfer(master, 1);
751 dw_i3c_master_enqueue_xfer(master, xfer);
753 dw_i3c_master_dequeue_xfer(master, xfer);
766 struct dw_i3c_master *master = to_dw_i3c_master(m);
773 ret = dw_i3c_ccc_get(master, ccc);
775 ret = dw_i3c_ccc_set(master, ccc);
782 struct dw_i3c_master *master = to_dw_i3c_master(m);
789 olddevs = ~(master->free_pos);
792 for (pos = 0; pos < master->maxdevs; pos++) {
800 master->devs[pos].addr = ret;
806 master->regs +
807 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
810 xfer = dw_i3c_master_alloc_xfer(master, 1);
814 pos = dw_i3c_master_get_free_pos(master);
821 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) |
828 dw_i3c_master_enqueue_xfer(master, xfer);
830 dw_i3c_master_dequeue_xfer(master, xfer);
832 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
835 for (pos = 0; pos < master->maxdevs; pos++) {
837 i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr);
851 struct dw_i3c_master *master = to_dw_i3c_master(m);
859 if (i3c_nxfers > master->caps.cmdfifodepth)
869 if (ntxwords > master->caps.datafifodepth ||
870 nrxwords > master->caps.datafifodepth)
873 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
904 dw_i3c_master_enqueue_xfer(master, xfer);
906 dw_i3c_master_dequeue_xfer(master, xfer);
926 struct dw_i3c_master *master = to_dw_i3c_master(m);
929 pos = dw_i3c_master_get_free_pos(master);
933 master->regs +
934 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
936 master->devs[data->index].addr = 0;
937 master->free_pos |= BIT(data->index);
940 master->devs[pos].addr = dev->info.dyn_addr;
941 master->free_pos &= ~BIT(pos);
945 master->regs +
946 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
948 master->devs[data->index].addr = dev->info.dyn_addr;
956 struct dw_i3c_master *master = to_dw_i3c_master(m);
960 pos = dw_i3c_master_get_free_pos(master);
969 master->devs[pos].addr = dev->info.dyn_addr ? : dev->info.static_addr;
970 master->free_pos &= ~BIT(pos);
973 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr),
974 master->regs +
975 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
984 struct dw_i3c_master *master = to_dw_i3c_master(m);
987 master->regs +
988 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
991 master->devs[data->index].addr = 0;
992 master->free_pos |= BIT(data->index);
1002 struct dw_i3c_master *master = to_dw_i3c_master(m);
1010 if (i2c_nxfers > master->caps.cmdfifodepth)
1020 if (ntxwords > master->caps.datafifodepth ||
1021 nrxwords > master->caps.datafifodepth)
1024 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers);
1051 dw_i3c_master_enqueue_xfer(master, xfer);
1053 dw_i3c_master_dequeue_xfer(master, xfer);
1064 struct dw_i3c_master *master = to_dw_i3c_master(m);
1068 pos = dw_i3c_master_get_free_pos(master);
1077 master->devs[pos].addr = dev->addr;
1078 master->free_pos &= ~BIT(pos);
1083 master->regs +
1084 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1093 struct dw_i3c_master *master = to_dw_i3c_master(m);
1096 master->regs +
1097 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1100 master->devs[data->index].addr = 0;
1101 master->free_pos |= BIT(data->index);
1110 struct dw_i3c_master *master = to_dw_i3c_master(m);
1117 spin_lock_irqsave(&master->devs_lock, flags);
1118 master->devs[data->index].ibi_dev = dev;
1119 spin_unlock_irqrestore(&master->devs_lock, flags);
1128 struct dw_i3c_master *master = to_dw_i3c_master(m);
1131 spin_lock_irqsave(&master->devs_lock, flags);
1132 master->devs[data->index].ibi_dev = NULL;
1133 spin_unlock_irqrestore(&master->devs_lock, flags);
1139 static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master,
1147 dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx);
1149 spin_lock_irqsave(&master->devs_lock, flags);
1150 reg = readl(master->regs + dat_entry);
1158 master->platform_ops->set_dat_ibi(master, dev, enable, ®);
1159 writel(reg, master->regs + dat_entry);
1161 reg = readl(master->regs + IBI_SIR_REQ_REJECT);
1166 bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK);
1171 writel(reg, master->regs + IBI_SIR_REQ_REJECT);
1174 reg = readl(master->regs + INTR_STATUS_EN);
1178 writel(reg, master->regs + INTR_STATUS_EN);
1180 reg = readl(master->regs + INTR_SIGNAL_EN);
1184 writel(reg, master->regs + INTR_SIGNAL_EN);
1187 spin_unlock_irqrestore(&master->devs_lock, flags);
1194 struct dw_i3c_master *master = to_dw_i3c_master(m);
1197 dw_i3c_master_set_sir_enabled(master, dev, data->index, true);
1202 dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
1211 struct dw_i3c_master *master = to_dw_i3c_master(m);
1218 dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
1231 static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master,
1237 readl(master->regs + IBI_QUEUE_STATUS);
1240 static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master,
1264 spin_lock_irqsave(&master->devs_lock, flags);
1265 idx = dw_i3c_master_get_addr_pos(master, addr);
1267 dev_dbg_ratelimited(&master->base.dev,
1272 dev = master->devs[idx].ibi_dev;
1274 dev_dbg_ratelimited(&master->base.dev,
1282 dev_dbg_ratelimited(&master->base.dev,
1288 dev_dbg_ratelimited(&master->base.dev,
1295 dw_i3c_master_read_ibi_fifo(master, slot->data, len);
1300 spin_unlock_irqrestore(&master->devs_lock, flags);
1305 dw_i3c_master_drain_ibi_queue(master, len);
1307 spin_unlock_irqrestore(&master->devs_lock, flags);
1314 static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master)
1319 reg = readl(master->regs + QUEUE_STATUS_LEVEL);
1325 reg = readl(master->regs + IBI_QUEUE_STATUS);
1328 dw_i3c_master_handle_ibi_sir(master, reg);
1331 dev_info(&master->base.dev,
1334 dw_i3c_master_drain_ibi_queue(master, len);
1341 struct dw_i3c_master *master = dev_id;
1344 status = readl(master->regs + INTR_STATUS);
1346 if (!(status & readl(master->regs + INTR_STATUS_EN))) {
1347 writel(INTR_ALL, master->regs + INTR_STATUS);
1351 spin_lock(&master->xferqueue.lock);
1352 dw_i3c_master_end_xfer_locked(master, status);
1354 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
1355 spin_unlock(&master->xferqueue.lock);
1358 dw_i3c_master_irq_handle_ibis(master);
1415 int dw_i3c_common_probe(struct dw_i3c_master *master,
1421 if (!master->platform_ops)
1422 master->platform_ops = &dw_i3c_platform_ops_default;
1424 master->regs = devm_platform_ioremap_resource(pdev, 0);
1425 if (IS_ERR(master->regs))
1426 return PTR_ERR(master->regs);
1428 master->core_clk = devm_clk_get(&pdev->dev, NULL);
1429 if (IS_ERR(master->core_clk))
1430 return PTR_ERR(master->core_clk);
1432 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
1434 if (IS_ERR(master->core_rst))
1435 return PTR_ERR(master->core_rst);
1437 ret = clk_prepare_enable(master->core_clk);
1441 reset_control_deassert(master->core_rst);
1443 spin_lock_init(&master->xferqueue.lock);
1444 INIT_LIST_HEAD(&master->xferqueue.list);
1446 writel(INTR_ALL, master->regs + INTR_STATUS);
1450 dev_name(&pdev->dev), master);
1454 platform_set_drvdata(pdev, master);
1457 ret = readl(master->regs + QUEUE_STATUS_LEVEL);
1458 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
1460 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL);
1461 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret);
1463 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER);
1464 master->datstartaddr = ret;
1465 master->maxdevs = ret >> 16;
1466 master->free_pos = GENMASK(master->maxdevs - 1, 0);
1469 if (master->ibi_capable)
1472 ret = i3c_master_register(&master->base, &pdev->dev, ops, false);
1479 reset_control_assert(master->core_rst);
1482 clk_disable_unprepare(master->core_clk);
1488 void dw_i3c_common_remove(struct dw_i3c_master *master)
1490 i3c_master_unregister(&master->base);
1492 reset_control_assert(master->core_rst);
1494 clk_disable_unprepare(master->core_clk);
1502 struct dw_i3c_master *master;
1504 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1505 if (!master)
1508 return dw_i3c_common_probe(master, pdev);
1513 struct dw_i3c_master *master = platform_get_drvdata(pdev);
1515 dw_i3c_common_remove(master);
1519 { .compatible = "snps,dw-i3c-master-1.00a", },
1528 .name = "dw-i3c-master",